Cirrus-logic EP93xx Manuel d'utilisateur télécharger pdf (Page 133)

DS785UM1 5-7

System Controller

EP93xx User’s Guide

Figure 5-3. Bus Clock Generation

There are some limitations of each clock. FCLK must be <=200 MHz, HCLK<=100 MHz and

PCLK<=50 MHz and FCLK >= HCLK > PCLK. Refer to register, “ClkSet1” on page 5-18, for

the detailed configuration information regarding the divider bit fields.

PLL1External Clock

FCLK Divide = 1, 2, 4, 8, 16

HCLK Divide = 1, 2, 4, 5, 6,

For 2nd stage dividers:

PCLK Divide = 1, 2, 4, 8

MAX = 100 MHz

MAX = 250 MHz

MAX = 500 MHz

MAX = 50 MHz

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Cirrus-logic EP93xx Manuel d'utilisateur Page 133