Cirrus-logic EP93xx Manuel d'utilisateur

Naviguer en ligne ou télécharger Manuel d'utilisateur pour Matériel Cirrus-logic EP93xx. Cirrus Logic EP93xx User Manual Manuel d'utilisatio

  • Télécharger
  • Ajouter à mon manuel
  • Imprimer
  • Page
    / 824
  • Table des matières
  • MARQUE LIVRES
  • Noté. / 5. Basé sur avis des utilisateurs
Vue de la page 0
©Copyright 2007 Cirrus Logic, Inc. SEP 2007
DS785UM1
http://www.cirrus.com
EP93XX
ARM
®
9 Embedded Processor Family
EP93xx
Users Guide
Vue de la page 0
1 2 3 4 5 6 ... 823 824

Résumé du contenu

Page 1 - EP93xx

©Copyright 2007 Cirrus Logic, Inc. SEP 2007DS785UM1http://www.cirrus.comEP93XX ARM®9 Embedded Processor FamilyEP93xx User’s Guide

Page 2

x ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s Guide 14.2.1.9 Interrupt Generation Logic ...

Page 3 - Contents

3-30 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Move 64-bit Integer from AccumulatorDescription:Saturates an

Page 4

DS785UM1 3-31Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Move from Control/Status Register to MaverickCrunch Register

Page 5

3-32 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Convert Single Precision Floating Point to Double Precision

Page 6

DS785UM1 3-33Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Convert 32-bit Integer to Double Precision Floating PointDes

Page 7

3-34 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Convert Single Precision Floating Point to 32-bit IntegerDes

Page 8

DS785UM1 3-35Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Bit Definitions:CRd: Destination register CRn: Source regist

Page 9

3-36 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Shift 32-bit Integer ImmediateDefinition:Shift a 32-bit inte

Page 10 - EP93xx User’s Guide

DS785UM1 3-37Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Mnemonic:CFCMPS<cond> Rd, CRn, CRmBit Definitions:CRn:

Page 11

3-38 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Rd: Destination ARM register. If Rd = 15, destination is AR

Page 12 - Chapter 21. I

DS785UM1 3-39Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Bit Definitions:CRd: Destination register CRn: Source regist

Page 13

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. xiEP93xx User’s GuideChapter 17. IrDA ...

Page 14

3-40 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Double Precision Floating Point AddDescription:Adds two doub

Page 15

DS785UM1 3-41Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Single Precision Floating Point MultiplyDescription:Multipli

Page 16

3-42 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide33364-bit Integer Absolute ValueDescription:Computes the absolu

Page 17

DS785UM1 3-43Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Mnemonic:CFADD32<cond> CRd, CRn, CRmBit Definitions:CR

Page 18

3-44 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Bit Definitions:CRd: Destination register CRn: Minuend regis

Page 19

DS785UM1 3-45Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Bit Definitions:CRd: Destination/addend register CRn: Multip

Page 20

3-46 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide33332-bit Integer Multiply-Subtract, Result to AccumulatorDescr

Page 21

DS785UM1 3-47Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide33332-bit Integer Multiply-Subtract from AccumulatorDescription

Page 22 - Revision History

3-48 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333

Page 23 - 17Preface

DS785UM1 4-1Copyright 2007 Cirrus Logic 444Chapter 44Boot ROM 4.1 IntroductionThe Boot ROM allows a program or OS to boot from the following devices:

Page 24

xii ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s GuideChapter 20. Real Time Clock With Software Trim ...

Page 25 - P.4 Notational Conventions

4-2 DS785UM1Copyright 2007 Cirrus LogicBoot ROMEP93xx User’s Guide444Note that the code retrieved via UART1 and the SPI Serial Flash is not intended t

Page 26 - P.5 Register Example

DS785UM1 4-3Copyright 2007 Cirrus Logic Boot ROMEP93xx User’s Guide4448. If it is not a Serial Download, attempt to read from SPI Serial Flash (see Fi

Page 27 - DS785UM1 P-5

4-4 DS785UM1Copyright 2007 Cirrus LogicBoot ROMEP93xx User’s Guide444 Figure 4-1. Flow Chart of Boot ROM Software 4.2 Boot OptionsTable 4-1 show

Page 28 - P-6 DS785UM1

DS785UM1 4-5Copyright 2007 Cirrus Logic Boot ROMEP93xx User’s Guide444Note: ASYNC boot mode is the preferred boot mode type for new designs.Table 4-1.

Page 29 - 1Introduction

4-6 DS785UM1Copyright 2007 Cirrus LogicBoot ROMEP93xx User’s Guide444 4.2.1 UART BootMake sure that the boot configuration pins (see Table 5-1 on pag

Page 30 - Memory Management Unit

DS785UM1 4-7Copyright 2007 Cirrus Logic Boot ROMEP93xx User’s Guide4440x3000_10000x6000_00000x7000_0000Code execution will start at address FLASH base

Page 31 - Peripheral Bus (APB)

4-8 DS785UM1Copyright 2007 Cirrus LogicBoot ROMEP93xx User’s Guide4443. Run the internal boot code and boot from FLASH4. Set the PLL back to use the e

Page 32

DS785UM1 5-1Copyright 2007 Cirrus Logic 555Chapter 55System Controller 5.1 IntroductionThe System Controller (Syscon) provides:• Clock control• Power

Page 33 - Introduction

5-2 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555certain system variables such as RTC, SDRAM refresh control/global confi

Page 34 - 1-6 DS785UM1

DS785UM1 5-3Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555The normal boot function is described in Chapter 4 on page 4-1.Serial b

Page 35 - 1.4.2 MaverickCrunch

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. xiiiEP93xx User’s Guide 23.5 Configuring the SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 36 - 1.4.3 MaverickKey

5-4 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555Note: ASYNC boot mode is the preferred boot mode type for new designs.

Page 37 - DS785UM1 1-9

DS785UM1 5-5Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555Both PLLs are software programmable (each value is defined in “ClkSet1”

Page 38 - 1.4.13 PCMCIA Interface

5-6 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555 Figure 5-2. Clock Generation System 5.1.5.2.1 Bus Clock GenerationFigu

Page 39 - Chapter 2

DS785UM1 5-7Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555 Figure 5-3. Bus Clock GenerationThere are some limitations of each cl

Page 40 - 2.2.3 Operations

5-8 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555Even though FCLK is the usual CPU clock, HCLK can optionally be used ins

Page 41 - 2.2.3.1 ARM9TDMI Core

DS785UM1 5-9Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555 5.1.5.3 Steps for Clock ConfigurationThe boot ROM must contain code th

Page 42 - 2-4 DS785UM1

5-10 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555 HCLK to the USB Hosts can be gated off as well to further save power.

Page 43 - 2.2.3.2.3 MMU Enable

DS785UM1 5-11Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555 Figure 5-4. Power States and Transitions 5.1.6.2.1 Power-on-Reset

Page 44 - 2.2.3.3.2 Data Cache Enable

5-12 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555set. One example of this is when a power-on-reset is applied and this r

Page 45 - DS785UM1 2-7

DS785UM1 5-13Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555 5.2 RegistersThis section contains the detailed register description

Page 46 - Figure 2-3. Main Data Paths

xiv ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s GuideChapter 27. IDE Interface...

Page 47 - 2.2.8 Bus Arbitration

5-14 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555Register DescriptionsPwrSts Address:0x8093_0000 - Read OnlyDefinition

Page 48

DS785UM1 5-15Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555RSTFLG: Reset flag. This bit is set if the user reset button has beenp

Page 49 - 2.3 AHB Decoder

5-16 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555DMA M2M/P CHx: These bits enable the clocks to the DMA controllerchanne

Page 50 - 2.3.2 AHB-to-APB Bridge

DS785UM1 5-17Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555Standby and Halt Address:Standby - 0x8093_000C - Read OnlyHalt - 0x8

Page 51 - 2.3.4 Register Definitions

5-18 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555STFClr Address:0x8093_001C - WriteDefinition:Writing to the STFClr loca

Page 52

DS785UM1 5-19Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555PLL1_X2FBD2: These 6 register bits set the first feedback divider bits

Page 53

5-20 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555nBYP1: This bit selects the clock source for the processor clockdivide

Page 54 - 2.3.5 Memory Map

DS785UM1 5-21Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555PLL2_X2FBD2: These 6 register bits set the first feedback divider bits

Page 55 - 2.3.6 Internal Register Map

5-22 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555ScratchReg0, ScratchReg1 Address:ScratchReg0 - 0x8093_0040, Read/Writ

Page 56

DS785UM1 5-23Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555BusMstrArb Address:0x8093_0054 - Read/WriteDefinition:The Bus Master a

Page 57

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. xvEP93xx User’s Guide Figure 4-1. Flow Chart of Boot ROM Software...

Page 58

5-24 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555DMA_ENFIQ: When set the arbiter will degrant DMA from the AHB busand wi

Page 59 - End Of Line Offset value N

DS785UM1 5-25Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555DeviceCfg Address:0x8093_0080 - Read/Write, Software lockedDefault:0

Page 60

5-26 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555I2SonAC97: Audio - I2S on AC97 pins. The I2S block uses the AC97pins. S

Page 61

DS785UM1 5-27Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide5550 - GPIO Port H used for IDE1 - GPIO Port H used for GPIOHC3IN: HDLC3

Page 62

5-28 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555A1onG: I2S Audio Port 1 on GPIO. 1 - I2S Port 1 pins are mapped to EGPI

Page 63

DS785UM1 5-29Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555SWRST: Software reset. A one to zero transition of this bit initiatesa

Page 64

5-30 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555MIRClkDiv Address:0x8093_0088 - Read/Write, Software lockedDefault:0x

Page 65

DS785UM1 5-31Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555I2SClkDiv Address:0x8093_008C - Read/Write, Software lockedDefault:0

Page 66

5-32 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555SDIV: SCLK divide select. 1 - SCLK = MCLK / 4, 0 - SCLK = MCLK / 2.MENA

Page 67

DS785UM1 5-33Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555ADIV: ADC clock divider value. 0 - ADC Clock is divide-by-16 from the

Page 68

xvi ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s Guide Figure 10-4. Edge-triggered DREQ Mode...

Page 69

5-34 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555SysCfg Address:0x8093_009C - Read/Write, Software lockedDefault:0x0000_

Page 70

DS785UM1 5-35Copyright 2007 Cirrus Logic System ControllerEP93xx User’s Guide555LCSn1, LCSn2: Define Watchdog startup action:00 - Watchdog disabled, R

Page 71 - 3MaverickCrunch Co-Processor

5-36 DS785UM1Copyright 2007 Cirrus LogicSystem ControllerEP93xx User’s Guide555

Page 72 - 3-2 DS785UM1

DS785UM1 6-1Copyright 2007 Cirrus Logic 666Chapter 66Vectored Interrupt Controller 6.1 IntroductionThe EP93xx processors contain two cascaded Vectore

Page 73 - 63 62 55 32 31 0

6-2 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666 Figure 6-1. Vectored Interrupt Controller Block Diagram 6.1

Page 74 - 3-4 DS785UM1

DS785UM1 6-3Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666Any 16 of the 32 interrupts (per VIC) can be designated as

Page 75

6-4 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666 6.1.3 Interrupt DetailsDetails of the interrupts described

Page 76 - 3.1.6 Comparisons

DS785UM1 6-5Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666TC1UI Timer Counter 1 Under Flow Interrupt. When Timer Coun

Page 77

6-6 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666UART1TXINTR1 UART 1 Transmit Interrupt. See Chapter 14, &qu

Page 78 - 3.2.1 Example 1

DS785UM1 6-7Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666CLK1HZ 1 Hz clock interrupt. See Chapter 20, "Real Ti

Page 79 - 3.2.2 Example 2

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. xviiEP93xx User’s Guide Figure 25-1. Different Types of Touch Screens ...

Page 80 - 3.3 DSPSC Register

6-8 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666INT_DSP ARM Core interrupt. GPIOINTR Combined Interrupt fr

Page 81 - DS785UM1 3-11

DS785UM1 6-9Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666Note: The Reset Values of the VICxPeriphID[3:0] registers

Page 82 - 3-12 DS785UM1

6-10 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666Definition:IRQ Status Register. The VICxIRQStatus register

Page 83 - DS785UM1 3-13

DS785UM1 6-11Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666Definition:The VICxRawIntr register provides the status of

Page 84

6-12 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666Definition:Interrupt Enable Register. The VICxIntEnable reg

Page 85

DS785UM1 6-13Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666Default: Don’t CareDefinition:Software Interrupt Register.

Page 86

6-14 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666Definition:Protection Enable Register. The VICxProtection r

Page 87

DS785UM1 6-15Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666If you are not using the priority level in the VIC, write

Page 88

6-16 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666VICxVectAddr7,VICxVectAddr8,VICxVectAdd9,VICxVectAddr10,VIC

Page 89

DS785UM1 6-17Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666VIC2VectAddr6: 0x800C_0118 - Read/WriteVIC2VectAddr7: 0x80

Page 90

xviii ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s GuideTable 3-6. LDC/STC Opcode Map ...

Page 91 - Immediate post-indexed 1

6-18 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666VICxVectCntl15 Address:VIC1VectCntl0: 0x800B_0200 - Read

Page 92

DS785UM1 6-19Copyright 2007 Cirrus Logic Vectored Interrupt ControllerEP93xx User’s Guide666Note: Vectored interrupts are only generated if the inter

Page 93

6-20 DS785UM1Copyright 2007 Cirrus LogicVectored Interrupt ControllerEP93xx User’s Guide666

Page 94 - 3.5.2 Move Instructions

DS785UM1 7-1Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Chapter 77Raster Engine Wit

Page 95

7-2 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777The Raster engine also suppo

Page 96

DS785UM1 7-3Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Since the frame buffer is s

Page 97

7-4 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777to one pixel combination bli

Page 98

DS785UM1 7-5Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777most significant location o

Page 99

7-6 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 7.3.5 Frame Buffer Memory

Page 100

DS785UM1 7-7Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777brightness control. The Bri

Page 101

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. xixEP93xx User’s GuideTable 8-2. bpp Memory Organization...

Page 102

7-8 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 Figure 7-1. Raster Engine B

Page 103

DS785UM1 7-9Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777register, “VidScrnPage” on

Page 104

7-10 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777words on both the upper and

Page 105 - 3.5.5 Shift Instructions

DS785UM1 7-11Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777this mode will cause an ob

Page 106 - 3.5.6 Compare Instructions

7-12 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777data into the unused LSBs o

Page 107

DS785UM1 7-13Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Table 7-3. Output Pixel T

Page 108

DS785UM1 7-14Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777*These bits are an ORed c

Page 109

DS785UM1 7-15Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 7.4.8 Grayscale/Color Ge

Page 110

7-16 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Assuming that pixel input v

Page 111

DS785UM1 7-17Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 7.4.8.7 Grayscale Look-Up

Page 112

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. iiEP93xx User’s GuideContacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirr

Page 113

xx ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s GuideTable 11-1. Frame Bandwidth Allocation ...

Page 114

7-18 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Where FRAME[1:0] = FRAME_CN

Page 115

DS785UM1 7-19Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777At clock 0, the HCNT, VCNT

Page 116

7-20 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777The values in between full

Page 117 - Bit Definitions:

DS785UM1 7-21Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 Figure 7-4. Sample Matrix

Page 118 - Copyright 2007 Cirrus Logic

7-22 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Assuming the 3 bit input pa

Page 119 - 4Boot ROM

DS785UM1 7-23Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Please note that as the fr

Page 120 - 4.1.2.2 Boot Algorithm

7-24 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 Figure 7-8. Three and Four

Page 121 - 4.1.2.3 Flowchart

DS785UM1 7-25Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777“Start” is the beginning w

Page 122 - 4.2 Boot Options

7-26 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777The X location value contro

Page 123 - CSn[7:6] value:

DS785UM1 7-27Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777CLINSSix bits select the h

Page 124 - 4.2.3 FLASH Boot

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. xxiEP93xx User’s GuideTable 17-5. UART2 / IrDA Modes ...

Page 125

7-28 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 7.4.10 Video TimingThe vid

Page 126 - 7. Run from SDRAM

DS785UM1 7-29Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 Figure 7-9. Progressive/D

Page 127 - 5System Controller

7-30 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 Figure 7-10. Interlaced Vi

Page 128

DS785UM1 7-31Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 7.4.10.1 Setting the Vide

Page 129

7-32 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777VLineStep = 640 x 4bpp/32 7

Page 130 - 5.1.5 Clock Control

DS785UM1 7-33Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 7.4.11.2.1 PattrnMask Re

Page 131 - System Controller

7-34 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777If the LUT is enabled, the

Page 132 - 5-6 DS785UM1

DS785UM1 7-35Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide7771. The MSB is dropped2.The

Page 133 - DS785UM1 5-7

7-36 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777 7.5 RegistersTable 7-12.

Page 134

DS785UM1 7-37Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Note: The raster engine re

Page 135 - 5.1.6 Power Management

xxii ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s GuideTable 28-5. GPIO Register Address Map...

Page 136 - 5.1.6.2 System Power States

7-38 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Vertical Frame Timing Regis

Page 137 - Standby Run Halt

DS785UM1 7-39Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777When the Vertical counter

Page 138 - 5.1.7 Interrupt Generation

7-40 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777VBlankStrtStop Address: 0x8

Page 139 - 5.2 Registers

DS785UM1 7-41Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777VClkStrtStop Address: 0x80

Page 140 - PwrSts

7-42 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Horizontal Frame Timing Reg

Page 141 - Bit Descriptions:

DS785UM1 7-43Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777The STOP value is the hori

Page 142 - 5-16 DS785UM1

7-44 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777STRT: Start - Read/WriteThe

Page 143 - Standby and Halt

DS785UM1 7-45Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777HClkStrtStop Address: 0x80

Page 144

7-46 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Frame Buffer Memory Configu

Page 145 - DS785UM1 5-19

DS785UM1 7-47Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777PAGE: Video Screen Half-p

Page 146 - ClkSet2

DS785UM1 P-1Copyright 2007 Cirrus Logic PPPChapter P17Preface P.1 About the EP93xx User’s GuideThis EP93xx User’s Guide describes the architecture, h

Page 147 - DS785UM1 5-21

7-48 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777LEN: Length - Read/WriteThe

Page 148 - APBWait

DS785UM1 7-49Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777LineCarry Address: 0x8003_

Page 149 - BusMstrArb

7-50 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777If the Offset value is 0x0,

Page 150 - BootModeClr

DS785UM1 7-51Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777VideoAttribs Address: 0x80

Page 151 - DeviceCfg

7-52 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777DHORZ: Double Horizontal -

Page 152

DS785UM1 7-53Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777V_CSYNC --> D7 (Smart P

Page 153 - DS785UM1 5-27

7-54 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide7771 - Pixel data output chang

Page 154 - 5-28 DS785UM1

DS785UM1 7-55Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777PCLKEN: Pixel Clock Enable

Page 155 - VidClkDiv

7-56 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777ACRateAddress: 0x8003_0214D

Page 156 - MIRClkDiv

DS785UM1 7-57Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777This field should be writt

Page 157 - I2SClkDiv

P-2 DS785UM1Copyright 2007 Cirrus Logic PrefaceEP93xx User’s GuidePPP6: Vectored Interrupt Controller X X X X X7: Raster Engine with Analog and LCD In

Page 158 - KeyTchClkDiv

7-58 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Writing a Dual Scan value t

Page 159 - CHIP_ID

DS785UM1 7-59Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777S: Shift - Read/WriteThe

Page 160 - Default:

7-60 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777ParllIfOutAddress: 0x8003_0

Page 161 - SysSWLock

DS785UM1 7-61Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777P3 --> D3P[2:0] -->

Page 162 - 5-36 DS785UM1

7-62 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Smart Panel R/W and RS sign

Page 163 - Chapter 6

DS785UM1 7-63Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Blink Control RegistersBli

Page 164 - 6.1.1 Interrupt Priority

7-64 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Bit Descriptions:RSVD: Res

Page 165

DS785UM1 7-65Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777PattrnMask Address: 0x8003

Page 166 - 6.1.3 Interrupt Details

7-66 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Bit Descriptions:RSVD: Res

Page 167 - Vectored Interrupt Controller

DS785UM1 7-67Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777CursorAdrReset Address: 0x

Page 168 - 6-6 DS785UM1

DS785UM1 P-3Copyright 2007 Cirrus LogicPrefaceEP93xx User’s GuidePPPNote:“X” means Function is included; “-” means Function is not included P.2 Relat

Page 169 - DS785UM1 6-7

7-68 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777CursorSizeAddress: 0x8003_0

Page 170 - from the respective base

DS785UM1 7-69Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide77700 - Display 1 word (16 pi

Page 171 - VICxIRQStatus

7-70 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777CursorXYLoc Address: 0x8003

Page 172 - VICxRawIntr

DS785UM1 7-71Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777The X Location value writt

Page 173 - VICxIntEnable

7-72 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777When Dual Scan mode is enab

Page 174 - VICxSoftInt

DS785UM1 7-73Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777When EN = ‘0’ and the 2-bi

Page 175 - VICxProtection

7-74 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Writing a Frame Counter Sel

Page 176 - VICxVectAddr

DS785UM1 7-75Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Writing ‘1’s to these Matr

Page 177

7-76 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Where: FRAME[1:0] = FRAME_C

Page 178

DS785UM1 7-77Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777ColorLUTAddress: 0x8003_04

Page 179

P-4 DS785UM1Copyright 2007 Cirrus Logic PrefaceEP93xx User’s GuidePPP• Registers are named using mixed upper and lower case alphanumeric, for example,

Page 180 - VICxVectCntl15

7-78 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Bit Descriptions:RSVD: Res

Page 181

DS785UM1 7-79Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777CLKEN: Clock Enable - Rea

Page 182 - 6-20 DS785UM1

7-80 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777Bit Descriptions:RSVD: Res

Page 183 - Timing and Interface

DS785UM1 7-81Copyright 2007 Cirrus Logic Raster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777The STRT value is the valu

Page 184

7-82 DS785UM1Copyright 2007 Cirrus LogicRaster Engine With Analog/LCD Integrated Timing and InterfaceEP93xx User’s Guide777

Page 185 - 7.2 Features

DS785UM1 8-1Copyright 2007 Cirrus Logic 888Chapter 88Graphics Accelerator 8.1 OverviewNote: The chapter applies only to the EP9307 and EP9315 proceso

Page 186 - Displays

8-2 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888 8.2.1 CopyIt is possible to copy data from the source memory to th

Page 187

DS785UM1 8-3Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide8882. Logical Destination 3. Transparency 8.2.2 Remapping The Graphic

Page 188

8-4 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888 8.3.1 Breshenham Line Draws Based on Breshenham's algorithm,

Page 189 - 7.3.7 Hardware Cursor

DS785UM1 8-5Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888 8.4.1 Memory Organization for 1 Bit Per Pixel (bpp)The 1 bpp stor

Page 190 - Interface)

DS785UM1 P-5Copyright 2007 Cirrus LogicPrefaceEP93xx User’s GuidePPPREV: Revision, reads chip Version number: 0 - Rev A, 1 - Rev B, 2 - Rev C, 3 - Rev

Page 191 - 7.4.2 Video FIFO

8-6 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888 8.4.4 Memory Organization for 16-Bits Per PixelThe 16 bpp storag

Page 192 - 7.4.4 Blink Function

DS785UM1 8-7Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888 8.4.5 Memory Organization for 24-Bits Per PixelThe 24 bpp packed o

Page 193 - 7.4.6 Color RGB Mux

8-8 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888 8.4.6 Memory Map AccessThe Graphics Accelerator has access to the

Page 194 - 7.4.7 Pixel Shift Logic

DS785UM1 8-9Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888If a Block Copy starts at pixel 3 and 10 pixels are to be copied, th

Page 195

8-10 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888memory and the other register, “DESTPIXELSTRT”, is used for the des

Page 196

DS785UM1 8-11Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888 8.5.2.2 8 BPP Word Layout For a Block Copy where 4 pixels are tran

Page 197

8-12 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888Let the starting SDRAM address of the destination image be 0x0044.

Page 198 - 7-16 DS785UM1

DS785UM1 8-13Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888Note:The word count for this example would be: 6 - 1 = 5 words, sin

Page 199

8-14 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide8883. Setup DESTLINELENGTH Register A. Determine how many pixels occup

Page 200

DS785UM1 8-15Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide8889. Setup BLKDESTWIDTH RegisterWrite ‘abs(X2 -X1) modulo 4096, minus

Page 201

P-6 DS785UM1Copyright 2007 Cirrus Logic PrefaceEP93xx User’s GuidePPP

Page 202

8-16 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888SPEL = [X2% 2 (pixel depth / 8-bit byte)] x 8 = [101% 2 (16-bits /

Page 203

DS785UM1 8-17Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888SPEL is the starting pixel position within the word that the pixel-

Page 204

8-18 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide8887. Setup BLOCKCTRL RegisterFor (example) 16-bit pixels and Mask AND

Page 205

DS785UM1 8-19Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888comprise the first scan line of the source image.For example, Table

Page 206 - 7.4.9 Hardware Cursor

8-20 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888refer to the note in Section 8.5.2.4 on page 8-12.E. Write the desi

Page 207 - 1514131211109876543210

DS785UM1 8-21Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888 8.6.4.1 Example of Block CopyTo achieve the following display and

Page 208 - 7-26 DS785UM1

8-22 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888 8.7 Registers Note: Graphics Accelerator registers are intended t

Page 209 - DS785UM1 7-27

DS785UM1 8-23Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888Register DescriptionsSRCPIXELSTRTAddress: 0x8004_0000 - Read/WriteD

Page 210 - 7.4.10 Video Timing

8-24 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888Default: 0x0000_0000Mask: 0x001F_001FDefinition: Destination Pixel

Page 211 - DS785UM1 7-29

DS785UM1 8-25Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888Default: 0x0000_0000Mask: 0xFFFF_FFFCDefinition: Block Source Word

Page 212 - 7-30 DS785UM1

DS785UM1 1-1Copyright 2007 Cirrus Logic 111Chapter 11Introduction 1.1 IntroductionThe EP93xx processors are highly integrated systems-on-a-chip that

Page 213 - DS785UM1 7-31

8-26 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888BLKSRCWIDTH Address: 0x8004_0010 - Read/WriteDefault: 0x0000_0000Ma

Page 214 - 7.4.11 Blink Logic

DS785UM1 8-27Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888The value in this field specifies the number of 32 bit words, minus

Page 215 - 7.4.11.3 Types of Blinking

8-28 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888For Line Draw functions, the method to determine the value of WIDTH

Page 216 - 888 Blinking:

DS785UM1 8-29Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888DESTLINELENGTH Address: 0x8004_0020 - Read/WriteDefault: 0x0000_000

Page 217 - 7.4.12 Color Mode Definition

8-30 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888BLOCKCTRL Address: 0x8004_0024 - Read/WriteDefault: 0x0000_0000Mask

Page 218 - No Read/Write 24 bits

DS785UM1 8-31Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888ERROR: Error Indicator - Read/Write1 - Bus error has occurred0 - No

Page 219

8-32 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888‘1’ - Pixel Expansion Mapping Function enabled‘0’ - Pixel Expansion

Page 220 - VSyncStrtStop

DS785UM1 8-33Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888DYDIR = ‘0’ - Down in YFor a Line Draw function:DXDIR = ‘1’ - If X2

Page 221 - VActiveStrtStop

8-34 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888TRANSPATTRN Address: 0x8004_0028 - Read/WriteDefault: 0x0000_0000Ma

Page 222 - VBlankStrtStop

DS785UM1 8-35Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888MASK: Mask - Read/WriteFor a Block Copy function, the value in thi

Page 223 - VClkStrtStop

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. iiiEP93xx User’s GuideContentsChapter Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 224 - HSyncStrtStop

1-2 DS785UM1Copyright 2007 Cirrus LogicIntroductionEP93xx User’s Guide111Note:“X” means that the function is included; “-” means that the function is

Page 225 - HActiveStrtStop

8-36 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888LINEINC Address: 0x8004_00343 - Read/WriteDefault: 0x0000_0000Mask:

Page 226 - HBlankStrtStop

DS785UM1 8-37Copyright 2007 Cirrus Logic Graphics AcceleratorEP93xx User’s Guide888Bit Descriptions:RSVD: Reserved - Unknown during readYINIT: Y Ini

Page 227 - HClkStrtStop

8-38 DS785UM1 Copyright 2007 Cirrus LogicGraphics AcceleratorEP93xx User’s Guide888If BG = ‘1’ in the BLOCKCTRL register, a ‘0’ causes a pixel fill fr

Page 228 - VidScrnHPage

DS785UM1 9-1Copyright 2007 Cirrus Logic 999Chapter 991/10/100 Mbps Ethernet LAN Controller 9.1 IntroductionThe Ethernet LAN Controller incorporates a

Page 229 - LineLength

9-2 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999The Descriptor Processor implements the Hardware Ada

Page 230 - VLineStep

DS785UM1 9-3Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999The RAM blocks are interleaved in the AHB address s

Page 231 - - Read/Write

9-4 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 Figure 9-2. Ethernet Frame / Packet Format (Type II

Page 232 - Brightness

DS785UM1 9-5Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.1.3 Packet Transmission ProcessThis section exp

Page 233 - VideoAttribs

9-6 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Complete state. Thus, the Carrier Deference state ma

Page 234 - 7-52 DS785UM1

DS785UM1 9-7Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.1.4 Transmit Back-OffRefer to Figure 9-3. Once

Page 235 - DS785UM1 7-53

DS785UM1 1-3Copyright 2007 Cirrus Logic IntroductionEP93xx User’s Guide111 Figure 1-2. EP9302 Block Diagram Figure 1-3. EP9307 Block Diagram5-Channel

Page 236 - 7-54 DS785UM1

9-8 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999The resultant 32 bit field is transmitted on the lin

Page 237 - RasterSWLock

DS785UM1 9-9Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.1.4.6 Hash FilterThe 64 bit Logical Address Filt

Page 238 - FIFOLevel

9-10 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999The relationship of RXCtl.MA and RXCtl.IAHA is show

Page 239 - PixelMode

DS785UM1 9-11Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999To comply with the standard, pause frames should o

Page 240

9-12 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999most PHYs require a preamble for access to the PHY&

Page 241

DS785UM1 9-13Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.1.4.11.4 Steps for PHY Startup1. Set the MDC C

Page 242 - ParllIfOut

9-14 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999of buffers as they are exchanged with the MAC. When

Page 243 - ParllIfIn

DS785UM1 9-15Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Receive Descriptor Format - First Word Definition:

Page 244 - 7-62 DS785UM1

9-16 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3 Receive Status QueueThe receive status queu

Page 245 - BlinkMask

DS785UM1 9-17Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 Figure 9-8. Receive Status Queue Receive status

Page 246 - BlinkPattrn

1-4 DS785UM1Copyright 2007 Cirrus LogicIntroductionEP93xx User’s Guide111 Figure 1-4. EP9312 Block Diagram Figure 1-5. EP9315 Block Diagram8-Wire Touc

Page 247 - BkgrndOffset

9-18 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999If both EOF and EOB bits are zero, the entry was ma

Page 248 - CursorAdrStart

DS785UM1 9-19Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999EOF: End Of Frame. When this bit is set, the assoc

Page 249 - CursorAdrReset

9-20 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999HTI: Hash Table Index. If the frame was accepted as

Page 250 - CursorSize

DS785UM1 9-21Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.2 Receive Flow Figure 9-9. Receive Flow Dia

Page 251 - CursorBlinkColor2

9-22 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Refer to the circled numbers in Figure 9-9. The det

Page 252 - CursorXYLoc

DS785UM1 9-23Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.4 Receive Descriptor Data/Status Flow Figur

Page 253 - CursorDScanLHYLoc

9-24 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.5 Receive Descriptor Example Figure 9-11. Re

Page 254 - CursorBlinkRateCtrl

DS785UM1 9-25Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.6 Receive Frame Pre-ProcessingThe MAC pre-p

Page 255 - 0x7, 0x15, 0x23, and 0x31

9-26 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.7 Transmit Descriptor Processor QueuesThe tr

Page 256 - 7-74 DS785UM1

DS785UM1 9-27Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 Figure 9-13. Transmit Descriptor Format and Data

Page 257

DS785UM1 1-5Copyright 2007 Cirrus Logic IntroductionEP93xx User’s Guide111Features of the EP93xx processors are: • ARM920T Core: • 200 MHz maximum run

Page 258 - LUTSwCtrl

9-28 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 Figure 9-14. Multiple Fragments Per Transmit Frame

Page 259 - VidSigRsltVal

DS785UM1 9-29Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Bit Descriptions:TBA: Transmit Buffer Address. The

Page 260 - VidSigCtrl

9-30 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TBL: Transmit Buffer Length. This field contains th

Page 261 - VSigStrtStop

DS785UM1 9-31Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 Figure 9-15. Transmit Status Queue Transmit St

Page 262 - HSigStrtStop

9-32 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.11 Transmit Status FormatOnly one Transmit S

Page 263 - SigClrStr

DS785UM1 9-33Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999NColl: Number of Collisions. This field contains t

Page 264 - 7-82 DS785UM1

9-34 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.12 Transmit Flow Figure 9-16. Transmit Flow

Page 265 - 8Graphics Accelerator

DS785UM1 9-35Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Refer to Figure 9-16. The detailed transmit flow i

Page 266 - 8.2.1 Copy

9-36 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.3.14 Transmit Descriptor Data/Status Flow Figu

Page 267 - 8.2.3 Block Fills

DS785UM1 9-37Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999 9.2.4 Interrupts 9.2.4.1 Interrupt ProcessingInt

Page 268

1-6 DS785UM1Copyright 2007 Cirrus LogicIntroductionEP93xx User’s Guide111- Block Copy- Block Fill• Touch Screen interface- 5-ADC in EP9301 and 9302 on

Page 269

9-38 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide99914.Wait for RxAct (BMSts) to be set, and then enque

Page 270

DS785UM1 9-39Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide9991. RxMiss - This bit indicates that the receive fr

Page 271

9-40 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide99910.Wait for TxAct in BMSts to be set and then write

Page 272 - 8.5 Register Programming

DS785UM1 9-41Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Control Register DescriptionRXCtl Address:0x8001_0

Page 273 - 8.5.2 Pixel End and Start

9-42 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Chip Reset:0x0000_0x0xRx Reset:0x0000_0000Soft Rese

Page 274 - 8.5.2.1 4 BPP Word Layout

DS785UM1 9-43Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RxFCE1: Rx Flow Control Enable, bit 1. Setting the

Page 275 - 8.5.2.3 16 BPP WORD Layout

9-44 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999IAHA: Individual Address Hash Accept. When set, rec

Page 276 - 8.5.2.4 24 BPP mode

DS785UM1 9-45Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Soft Reset:0x0000_0000Definition:Transmit Control

Page 277 - 8.6 Register Usage

9-46 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999PB: Pause Busy: This bit remains set as long as a p

Page 278

DS785UM1 9-47Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999The following procedure will correctly set the Sel

Page 279 - Graphics Accelerator

DS785UM1 1-7Copyright 2007 Cirrus Logic IntroductionEP93xx User’s Guide111• 16 in EP9312 only• 24 in EP9315 only 1.3 EP93xx Processor Applications Th

Page 280 - 8.6.3 Block Fill Function

9-48 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RESET: Soft Reset. This is an act-once bit. When se

Page 281 - DS785UM1 8-17

DS785UM1 9-49Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999DiagDa Address:0x8001_003C - Read/WriteChip Reset:

Page 282 - 8.6.4 Block Copy Function

9-50 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Bit Descriptions:GTC: General Timer Count, read onl

Page 283 - DS785UM1 8-19

DS785UM1 9-51Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999FCF Address:0x8001_0048 - Read/WriteChip Reset:0x0

Page 284 - Copyright 2007 Cirrus Logic

9-52 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide9995. Pause time = Transmit Pause Time (FCF) (2bytes)6

Page 285 - DS785UM1 8-21

DS785UM1 9-53Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999IndAd Address:0x8001_0050 through 0x8001_0055 - 6

Page 286 - 8.7 Registers

9-54 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999HashTbl Address:0x8001_0050 through 0x8001_0057 - 8

Page 287

DS785UM1 9-55Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TXCollCnt Address:0x8001_0070 - Read OnlyChip Rese

Page 288 - Mask: 0x001F_001F

9-56 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Definition:Receive Miss Count RegisterBit Descripti

Page 289 - BLKDESTSTRT

DS785UM1 9-57Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TestCtl Address:0x8001_0008 - Read/WriteChip Reset

Page 290 - SRCLINELENGTH

1-8 DS785UM1Copyright 2007 Cirrus LogicIntroductionEP93xx User’s Guide111processor simplifies the end-user’s programming task by using predefined co-p

Page 291 - BLKDESTWIDTH

9-58 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Address:0x8001_0024 - Read/WriteChip Reset:0x0000_0

Page 292 - BLKDESTHEIGHT

DS785UM1 9-59Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999MOIE: Receive Miss Overflow Interrupt Enable. If r

Page 293 - DESTLINELENGTH

9-60 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999IntStsP/IntStsC Address:0x8001_0028, for IntStsP -

Page 294 - 0 1 0 8 bits per pixel

DS785UM1 9-61Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RxMI: RxMI is set when a receive frame was discard

Page 295 - 1 0 1 not defined

9-62 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RxROI: When a runt frame is received with a CRC err

Page 296 - 8-32 DS785UM1

DS785UM1 9-63Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Definition:Global Interrupt Status RegisterBit Des

Page 297 - DS785UM1 8-33

9-64 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999GlIntROSts Address:0x8001_0068 - Read OnlyChip Re

Page 298 - BLOCKMASK

DS785UM1 9-65Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Bit Descriptions:RSVD: Reserved. Unknown During Re

Page 299 - BACKGROUND

9-66 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999PHYAD: PHY Address. This field defines which extern

Page 300 - LINEINIT

DS785UM1 9-67Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Soft Reset:0x0000_0000Definition:MII Status Regist

Page 301 - LINEPATTRN

DS785UM1 1-9Copyright 2007 Cirrus Logic IntroductionEP93xx User’s Guide111 1.4.5 Integrated Ethernet MAC Reduces BOM CostsThe EP93xx processors integ

Page 302 - 0x000F_FFFF

9-68 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999MT: Manual Transfer. Writing a one to this bit caus

Page 303 - Chapter 9

DS785UM1 9-69Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TxEn: Transmit Enable. Writing a one to Transmit E

Page 304 - 9.1.1.4 Address Space

9-70 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RxEn: Receive Enable. Writing a one to Receive Enab

Page 305 - 9.1.2 MAC Engine

DS785UM1 9-71Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RxAct: Receive Active. When this bit is set, the c

Page 306 - 9-4 DS785UM1

9-72 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RXDQBLen Address:0x8001_0094 - Read/WriteChip Reset

Page 307 - 9.1.3.1 Carrier Deference

DS785UM1 9-73Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Definition:Receive Descriptor Queue Current Length

Page 308 - 9-6 DS785UM1

9-74 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RXDEnq Address:0x8001_009C - Read/WriteChip Reset:0

Page 309 - 9.1.4 Transmit Back-Off

DS785UM1 9-75Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Chip Reset:0x0000_0000Soft Reset:UnchangedDefiniti

Page 310 - 9.1.4.3 Bit Order

9-76 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RXStsQBLen Address:0x8001_00A4 - Read/WriteChip Res

Page 311 - 9.1.4.6 Hash Filter

DS785UM1 9-77Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Definition:Receive Status Queue Current Length. Th

Page 312 - 9.1.4.8 Receive Flow Control

1-10 DS785UM1Copyright 2007 Cirrus LogicIntroductionEP93xx User’s Guide111bits wide, the SMC supports 8-bit, 16-bit, and 32-bit devices, and the SDRAM

Page 313 - 9.1.4.11 Accessing the MII

9-78 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RXStsEnq Address:0x8001_00AC - Read/WriteChip Reset

Page 314 - PHY's registers

DS785UM1 9-79Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Chip Reset:0x0000_0000Soft Reset:UnchangedDefiniti

Page 315 - 9.2 Descriptor Processor

9-80 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Bit Descriptions:TDBA: Transmit Descriptor Base Add

Page 316 - 9-14 DS785UM1

DS785UM1 9-81Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Soft Reset:UnchangedDefinition:Transmit Descriptor

Page 317

9-82 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TXDEnq Address:0x8001_00BC - Read/WriteChip Reset:0

Page 318 - 9.2.3 Receive Status Queue

DS785UM1 9-83Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide9990x0000_0000Soft Reset:UnchangedDefinition:Transmit

Page 319 - Receive Status Queue

9-84 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TXStsQCurLen Address:0x8001_00C6 - Read/Write. Note

Page 320 - Receive Status - First Word

DS785UM1 9-85Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999Definition:Transmit Status Queue Current Address.

Page 321 - DS785UM1 9-19

9-86 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RDST: Receive Data Soft Threshold. The hard and sof

Page 322 - Receive Status - Second Word

DS785UM1 9-87Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TDST: Transmit Data Soft Threshold. The hard and s

Page 323 - 9.2.3.2 Receive Flow

DS785UM1 2-1Copyright 2007 Cirrus Logic 222Chapter 22ARM920T Core and Advanced High-Speed Bus (AHB) 2.1 IntroductionThis chapter describes the ARM920

Page 324 - 9.2.3.3 Receive Errors

9-88 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999The hard and soft threshold work in exactly the sam

Page 325 - DS785UM1 9-23

DS785UM1 9-89Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999The hard and soft threshold work in exactly the sa

Page 326 - Receive Status

9-90 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999RDST: Receive Descriptor Soft Threshold. The hard a

Page 327 - DS785UM1 9-25

DS785UM1 9-91Copyright 2007 Cirrus Logic 1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TDST: Transmit Descriptor Soft Threshold. The hard

Page 328 - 9-26 DS785UM1

9-92 DS785UM1Copyright 2007 Cirrus Logic1/10/100 Mbps Ethernet LAN ControllerEP93xx User’s Guide999TST: Transmit Start Threshold. The transmit start t

Page 329 - DS785UM1 9-27

DS785UM1 10-1Copyright 2007 Cirrus Logic 101010Chapter 1010DMA Controller 10.1 IntroductionThe DMA Controller can be used to interface streams from 20

Page 330

10-2 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010• Five hardware requests for M2M transfers; 2 for external peripherals

Page 331

DS785UM1 10-3Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010The DMA controller memory-to-memory channels can also be used in “Memo

Page 332 - 9-30 DS785UM1

10-4 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010The transaction is initiated by a SSP or IDE request.This request is ma

Page 333 - DS785UM1 9-31

DS785UM1 10-5Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010occurred. If the ICE bit is not set, then the DMA flushes the last goo

Page 334 - Transmit Status

iv ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s Guide2.3.2 AHB-to-APB Bridge ...

Page 335 - DS785UM1 9-33

2-2 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.2.2 Block Diagram Figure 2-1. ARM920T B

Page 336 - 9.2.3.12 Transmit Flow

10-6 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010 10.1.5.2 Hardware Trigger Mode for Internal Peripherals (SSP and IDE)

Page 337 - 9.2.3.13 Transmit Errors

DS785UM1 10-7Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010The data received on each of the five peripheral receive DMA Rx Data b

Page 338 - 9-36 DS785UM1

10-8 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010CE: Channel (Peripheral) ErrorICE: CONTROL[6] - Ignore Channel Error. T

Page 339 - 9.2.5 Initialization

DS785UM1 10-9Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010 10.1.9.2 Data Transfer Initiation and TerminationThe DMA Controller i

Page 340 - 9.2.5.4 Other Processing

10-10 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010 10.1.10 M2M DMA Functional Description 10.1.10.1 M2M DMA Control Fini

Page 341 - DS785UM1 9-39

DS785UM1 10-11Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010No data transfers occur in this state. 10.1.10.1.3 DMA_MEM_RDThe DMA

Page 342 - 9.3 Registers

10-12 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010 10.1.10.1.5 DMA_BWC_WAITThe DMA M2M Control FSM enters the DMA_BWC_WA

Page 343 - 0x8001_0000 - Read/Write

DS785UM1 10-13Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010(which BCRx is free can be determined using the STATUS.Nextbuffer sta

Page 344

10-14 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010The DMA Controller initiates memory-to-memory transfers in the receive

Page 345 - DS785UM1 9-43

DS785UM1 10-15Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010• For a software-triggered M2M transfer, a memory-write is initiated

Page 346 - Chip Reset:

DS785UM1 2-3Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222A 16 kbyte instruction and a 16 kbyte data

Page 347 - Soft Reset:

10-16 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010When the DONE interrupt is set, the processor can then write a one to

Page 348 - SelfCtl

DS785UM1 10-17Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010Subsequent changes on DREQ are ignored until the pending request begi

Page 349 - DS785UM1 9-47

10-18 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010At the start of a receive or transmit data transfer, the AHB Master In

Page 350

DS785UM1 10-19Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010 10.1.12.1 Internal M2P/P2M Channel Rx Buffer DescriptorsOnly one Rx

Page 351 - DS785UM1 9-49

10-20 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010During normal operation, using the “fair” rotating priority scheme sho

Page 352 - 9-50 DS785UM1

DS785UM1 10-21Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010 10.2.2 Internal M2P/P2M Channel Register MapThe DMA Memory Map above

Page 353

10-22 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010Register DescriptionsCONTROLAddress:Channel Base Address + 0x0000 - Re

Page 354 - through 005F

DS785UM1 10-23Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010ABORT: This bit determines how the DMA Channel State machine behaves

Page 355 - 10), is only used as the

10-24 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010NOTE: The naming convention used for channels and ports is as follows

Page 356 - HashTbl

DS785UM1 10-25Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010INTERRUPT Address:Channel Base Address + 0x0004 - Read/WriteDefinitio

Page 357 - RXMissCnt

2-4 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.2.3.2 Memory Management UnitThe MMU prov

Page 358 - RXRuntCnt

10-26 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010STATUS Address:Channel Base Address + 0x000C - Read OnlyDefinition:Thi

Page 359 - TestCtl

DS785UM1 10-27Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010Current State: Indicates the state that the Channel FSM is currently

Page 360

10-28 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010REMAINAddress:Channel Base Address + 0x0014 - Read OnlyDefinition:The

Page 361 - DS785UM1 9-59

DS785UM1 10-29Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010MAXCNTx Address:MAXCNT0: Channel Base Address + 0x0020 - Read/WriteMA

Page 362 - IntStsP/IntStsC

10-30 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010CURRENTx Address:CURRENT0: Channel Base Address + 0x0028 - Read Only

Page 363 - DS785UM1 9-61

DS785UM1 10-31Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010Note:See Table 10-3 for Channel Base AddressesNote:* Write this locat

Page 364 - GlIntSts

10-32 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010of the source and destination addresses to avoid any problems in the c

Page 365 - GlIntMsk

DS785UM1 10-33Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010Example: if BWC = 1010b (indicating 1024 bytes, see Table 10-9, below

Page 366 - GlIntFrc

10-34 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010DAH: Destination Address Hold - This bit is used for external M2P tran

Page 367 - DS785UM1 9-65

DS785UM1 10-35Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010NFBIntEn: Setting this bit to “1” enables the generation of the NFB

Page 368 - MIIData

DS785UM1 2-5Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.2.3.2.3 MMU EnableEnabling the MMU all

Page 369 - DS785UM1 9-67

10-36 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010Definition:This is the interrupt status register. The register is read

Page 370 - 9-68 DS785UM1

DS785UM1 10-37Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010STATUS Address:Channel Base Address + 0x000C - Read/WriteDefinition:T

Page 371 - DS785UM1 9-69

10-38 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010CurrentState: Indicates the states that the M2M Channel Control FSM an

Page 372

DS785UM1 10-39Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010EOTS: End-Of-Transfer status (valid only if the DEOT/TC pin has been

Page 373 - RXDQBAdd

10-40 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010The NextBuffer status bit can be used in conjunction with the CurrentS

Page 374 - RXDQCurLen

DS785UM1 10-41Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010to indicate that the external device has requested service. The STATU

Page 375 - RXDCurAdd

10-42 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010For a double/multiple buffer transfer, the second buffer descriptor ca

Page 376 - RXBCA

DS785UM1 10-43Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010DAR_BASEx Address:DAR_BASE0: Channel Base Address + 0x002C- Read/Writ

Page 377 - RXStsQBAdd

10-44 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010Bit Descriptions:SAR_CURRENTx: Returns the current value of the channe

Page 378 - RXStsQCurLen

DS785UM1 10-45Copyright 2007 Cirrus Logic DMA ControllerEP93xx User’s Guide101010Address:0x8000_03C0 - Read/WriteDefinition:DMA Global Interrupt Regis

Page 379 - RXStsQCurAdd

2-6 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.2.3.3.2 Data Cache Enable• A write to b

Page 380 - RXHdrLen

10-46 DS785UM1Copyright 2007 Cirrus LogicDMA ControllerEP93xx User’s Guide101010Definition:DMA Channel Arbitration Register. This bit controls the DMA

Page 381 - TXDQBAdd

DS785UM1 11-1Copyright 2007 Cirrus Logic 111111Chapter 1111Universal Serial Bus Host Controller 11.1 IntroductionNote: The EP9301 and EP9302 processor

Page 382 - TXDQCurLen

11-2 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111The Client Software/USB Device and Host Controll

Page 383 - TXDQCurAdd

DS785UM1 11-3Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111 11.2.2 Host Controller Interface 11.2.2.1 Commu

Page 384 - TXStsQBAdd

11-4 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111 11.2.2.2 Data StructuresThe basic building bloc

Page 385 - TXStsQBLen

DS785UM1 11-5Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111scheduling the Endpoint Descriptor at the approp

Page 386 - TXStsQCurAdd

11-6 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111 Figure 11-5. Sample Interrupt Endpoint Schedule

Page 387 - RXBufThrshld

DS785UM1 11-7Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111A portion of the bandwidth is reserved for nonpe

Page 388 - TXBufThrshld

11-8 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111 11.2.4 Host Controller ResponsibilitiesThis sec

Page 389 - RXStsThrshld

DS785UM1 11-9Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111 Figure 11-6. USB Host Controller Block Diagram

Page 390 - TXStsThrshld

DS785UM1 2-7Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222• Latched address and control• A simple In

Page 391 - RXDThrshld

11-10 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111 11.2.5.4 HCI Master Block The HCI Master Block

Page 392 - TXDThrshld

DS785UM1 11-11Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111 11.3 RegistersThe Host Controller (HC) contain

Page 393 - MaxFrmLen

11-12 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111OpenHCI Implementation Specific RegistersThe Ro

Page 394 - 9-92 DS785UM1

DS785UM1 11-13Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111Definition:Controls the host controller’s opera

Page 395 - 10DMA Controller

11-14 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111BLE: BulkListEnable: This bit is set to enable

Page 396 - DMA Controller

DS785UM1 11-15Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111RWE: RemoteWakeupEnable: This bit is used by HC

Page 397 - 10.1.3 DMA Operations

11-16 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111CLF: ControlListFilled: This bit is used to ind

Page 398 - 10-4 DS785UM1

DS785UM1 11-17Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111HcInterruptStatus Address:0x8002_000CDefault:0x

Page 399 - DS785UM1 10-5

11-18 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111FNO: FrameNumberOverflow. This bit is set when

Page 400 - 10.1.7 Interrupt Interface

DS785UM1 11-19Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111FNO: FrameNumberOverflow. Enable interrupt gen

Page 401 - DS785UM1 10-7

2-8 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 Figure 2-3. Main Data PathsBefore an AMBA

Page 402 - 10.1.9.1.4 DMA_NEXT

11-20 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111FNO: FrameNumberOverflow: Disable interrupt ge

Page 403 - DS785UM1 10-9

DS785UM1 11-21Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111Default:0x0000_0000Definition:Physical address

Page 404 - 10.1.10.1.2 DMA_STALL

11-22 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111HcControlCurrentEDAddress:0x8002_0024Default:0x

Page 405 - 10.1.10.1.4 DMA_MEM_WR

DS785UM1 11-23Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111Physical address of the first endpoint descript

Page 406 - 10.1.10.2.2 DMA_BUF_ON

11-24 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111HcDoneHeadAddress:0x8002_0030Default:0x0000_000

Page 407 - 10.1.10.2.3 DMA_BUF_NEXT

DS785UM1 11-25Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111RSVD: Reserved. Unknown During Read. FI: Frame

Page 408 - 10-14 DS785UM1

11-26 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111FRT: FrameRemainingToggle. This bit is loaded

Page 409 - DS785UM1 10-15

DS785UM1 11-27Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide1111110x8002_0040Default:0x0000_0000Definition:Define

Page 410 - 10.1.10.6 Bandwidth Control

11-28 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111HcRhDescriptorA Address:0x8002_0048Default:0x02

Page 411 - 12345678

DS785UM1 11-29Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111NPS: NoPowerSwitching. These bits are used to

Page 412 - 10.1.12 Buffer Descriptors

DS785UM1 2-9Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222A write data bus is used to move data from

Page 413 - 10.1.13 Bus Arbitration

11-30 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111Default:0x0000_0000Definition:Describes the roo

Page 414 - 10.2 Registers

DS785UM1 11-31Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111RSVD: Reserved. Unknown During Read. LPS: (REA

Page 415 - Register

11-32 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111HcRhPortStatusx Address:HcRhPortStatus1 - 0x800

Page 416

DS785UM1 11-33Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111PES: (READ) PortEnableStatus. This bit indicat

Page 417 - DS785UM1 10-23

11-34 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111POCI: (READ) PortOverCurrentIndicator. This bi

Page 418

DS785UM1 11-35Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111(WRITE) SetPortPower: The HCD writes a “1” to s

Page 419 - INTERRUPT

11-36 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111OCIC: PortOverCurrentIndicatorChange. This bit

Page 420

DS785UM1 11-37Copyright 2007 Cirrus Logic Universal Serial Bus Host ControllerEP93xx User’s Guide111111USBHCISts Address:0x8002_0084 - Read/WriteDef

Page 421 - DS785UM1 10-27

11-38 DS785UM1 Copyright 2007 Cirrus LogicUniversal Serial Bus Host ControllerEP93xx User’s Guide111111

Page 422

DS785UM1 12-1Copyright 2007 Cirrus Logic 121212Chapter 1212Static Memory Controller 12.1 IntroductionNote: In the EP9301 and 9302 processors, the comm

Page 423 - MAXCNTx

2-10 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.2.8.1 Main AHB Bus Arbiter This Main AH

Page 424 - Name Access Bits Reset Value

12-2 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide121212The SMC has five main functions: 1. Memory bank selecting 2.

Page 425

DS785UM1 12-3Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212 Figure 12-1. 32-bit Read, 32-bit Memory, 0 Wait Cycles, RBL

Page 426 - 10-32 DS785UM1

12-4 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide121212 Figure 12-3. 16-bit Read, 16-bit Memory, RBLE = 1, WAITn Ac

Page 427 - BWC Bytes

DS785UM1 12-5Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212If the bit-width of an internal device that generates a read

Page 428 - 10-34 DS785UM1

12-6 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide1212121. These signals go directly to the inserted PC card.2. The

Page 429

DS785UM1 12-7Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212 Figure 12-5. Single PC Card InterfaceRUN nCF_MCBVD

Page 430

12-8 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide121212 12.4 PC Card Memory-Mode Enable SignalsPC Card memory-mode

Page 431

DS785UM1 12-9Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212Table 12-6. Accesses to 8-Bit Attribute / Common / IO Memory

Page 432 - 10-38 DS785UM1

12-10 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide121212 12.6 Registers 12.6.1 Bank Configuration RegistersSMCBCR[7

Page 433 - DS785UM1 10-39

DS785UM1 12-11Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212Bit Descriptions:RSVD: Reserved - Unknown During Read IDCY:

Page 434 - 10-40 DS785UM1

DS785UM1 2-11Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.2.8.2 SDRAM Slave ArbiterThe SDRAM Sla

Page 435

12-12 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide121212The number of wait cycles for each of the 2nd, 3rd, and 4th

Page 436 - SAR_BASEx

DS785UM1 12-13Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212EBIBRKDIS: EBI Break Disable - Read/WriteThe value written

Page 437 - SAR_CURRENTx

12-14 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide121212The data strobe assertion time is specified by (AA+1) HCLK

Page 438 - DMAGlInt

DS785UM1 12-15Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212The value written to this field specifies the minimum ‘numb

Page 439

12-16 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide1212120 - 8-bit wide Common space1 - 16-bit wide Common spaceAI:

Page 440

DS785UM1 12-17Copyright 2007 Cirrus Logic Static Memory ControllerEP93xx User’s Guide121212PCEN: PC Card Enable - Read/WriteWriting a “1” to this bit

Page 441 - Chapter 11

12-18 DS785UM1 Copyright 2007 Cirrus LogicStatic Memory ControllerEP93xx User’s Guide121212

Page 442 - 11.2.1 Data Transfer Types

DS785UM1 13-1Copyright 2007 Cirrus Logic 131313Chapter 1313SDRAM, SyncROM, and SyncFLASH Controller 13.1 IntroductionNote: In the EP9301 and 9302 proc

Page 443 - Shared RAM

13-2 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Length = 0x4 (32-bit wide memory bus) or Bur

Page 444 - 11.2.2.2 Data Structures

DS785UM1 13-3Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313it’s data outputs in the high impedance stat

Page 445 - Endpoint Poll Interval (ms)

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. vEP93xx User’s Guide4.2.5 Synchronous Memory Operation...

Page 446

2-12 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.3.2 AHB-to-APB BridgeThe AHB-to-APB Br

Page 447 - 11.2.3.4 Root Hub

13-4 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313the synchronous memory map. Refer to Table 1

Page 448 - 11.2.4.3 List Processing

DS785UM1 13-5Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide1313132Write a ‘1’ or ‘0’ to the External Bus Widt

Page 449 - 11.2.5.3 HCI Slave Block

13-6 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313 13.5 Programming Mode Register: SDRAM Or Sy

Page 450 - 11.2.5.7 List Processor

DS785UM1 13-7Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Note: “RFU” means Reserved for Future Use. T

Page 451 - 11.3 Registers

13-8 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313When using a 16-bit wide external memory bus

Page 452 - HcControl

DS785UM1 13-9Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313to the SyncFLASH register and the associated

Page 453

13-10 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313 13.8.2 Address/Data/Control Required by Me

Page 454 - 11-14 DS785UM1

DS785UM1 13-11Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313that AD23 is not used (needed) in either th

Page 455 - HcCommandStatus

DS785UM1 13-12Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Table 13-11. EP93xx SDRAM Address Ranges (

Page 456 - 11-16 DS785UM1

DS785UM1 13-13Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide13131316-Bit Wide Data Systems(Continued)0xN300_

Page 457 - HcInterruptStatus

DS785UM1 2-13Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222Note: Due to decoding optimization, the A

Page 458 - HcInterruptEnable

DS785UM1 13-14Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide13131332-Bit Wide Data Systems64 Mbit (32-bit wi

Page 459 - HcInterruptDisable

DS785UM1 13-15Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313256 Mbit (32-bit wide device) 13 x 8 x 4 b

Page 460 - HcPeriodCurrentED

DS785UM1 13-16Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Note: , the letter "N" represent

Page 461 - HcControlHeadED

DS785UM1 13-17Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313 13.9 RegistersThe Synchronous Memory contr

Page 462 - HcBulkHeadED

13-18 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Register DescriptionsGlConfig Address: 0x80

Page 463 - HcBulkCurrentED

DS785UM1 13-19Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313The CKE bit must be written to ‘0’ before t

Page 464 - HcFmInterval

13-20 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Writing a ‘1’ to this bit, in combination w

Page 465 - HcFmRemaining

DS785UM1 13-21Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Definition:The Refresh Timer register is us

Page 466 - HcPeriodicStart

13-22 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Latched nCS[7:6] pins values:Asynchronous (

Page 467 - HcLSThreshold

DS785UM1 13-23Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313Definition:The four device configuration re

Page 468 - HcRhDescriptorA

2-14 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222User mode in Thumb state limits access to

Page 469 - HcRhDescriptorB

13-24 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313When writing to a SyncFLASH device, only si

Page 470 - HcRhStatus

DS785UM1 13-25Copyright 2007 Cirrus Logic SDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313The value written to this bit specifies a s

Page 471 - DS785UM1 11-31

13-26 DS785UM1 Copyright 2007 Cirrus LogicSDRAM, SyncROM, and SyncFLASH ControllerEP93xx User’s Guide131313 The value written to this bit specifies t

Page 472 - HcRhPortStatusx

DS785UM1 14-1Copyright 2007 Cirrus Logic 141414Chapter 1414UART1 With HDLC and Modem Control Signals 14.1 IntroductionUART1 is the collection of a UAR

Page 473 - DS785UM1 11-33

14-2 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414The FIFOs can be programmed to be 1 byte dee

Page 474 - 11-34 DS785UM1

DS785UM1 14-3Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 Figure 14-1. UART Block DiagramAMBAAMBAAPB

Page 475 - DS785UM1 11-35

14-4 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.2.1.4 Baud Rate GeneratorThe baud rate g

Page 476 - USBCfgCtrl

DS785UM1 14-5Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.2.1.10 Synchronizing Registers and Logi

Page 477 - USBHCISts

14-6 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.2.2.1 Error BitsThree error bits are sto

Page 478 - 11-38 DS785UM1

DS785UM1 14-7Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.2.3 Interrupts There are five interrupt

Page 479 - 12Static Memory Controller

DS785UM1 2-15Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222• spsr: Saved Program Status Register con

Page 480 - WAITn must remain asserted

14-8 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414• If the FIFOs are disabled (have a depth of

Page 481 - Static Memory Controller

DS785UM1 14-9Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.4.1 Overview of HDLC ModesHDLC may oper

Page 482 - 12-4 DS785UM1

14-10 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414The receiver utilizes a digital PLL to sync

Page 483

DS785UM1 14-11Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.4.3 HDLC TransmitIn normal operation,

Page 484

14-12 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414When the last byte of data for a packet is

Page 485 - DS785UM1 12-7

DS785UM1 14-13Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414incoming address consisting entirely of “1

Page 486 - 12.5 PC Card Memory Mapping

14-14 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.4.8 DMA The DMA engine may be used with

Page 487

DS785UM1 14-15Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414The use of EGPIO[3] is determined by sever

Page 488 - 12.6 Registers

14-16 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414 14.5.2 Bus Bandwidth RequirementsThere are

Page 489

DS785UM1 14-17Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide14141414.1 RegistersUART Register DescriptionsUA

Page 490 - 12-12 DS785UM1

2-16 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222 2.3.5 Memory Map The memory map for Sync

Page 491 - PCAttribute

14-18 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414UART1RXSts Address:0x808C_0004 - Read/Write

Page 492 - PCCommon

DS785UM1 14-19Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414FE: Framing Error. When this bit is set to

Page 493

14-20 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414FEN: FIFO Enable.1 - Transmit and receive F

Page 494 - PCMCIACtrl

DS785UM1 14-21Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414Definition:UART Line Control Register Midd

Page 495 - DS785UM1 12-17

14-22 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414UART1Ctrl Address:0x808C_0014 - Read/WriteD

Page 496 - 12-18 DS785UM1

DS785UM1 14-23Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414Address:0x808C_0018 - Read OnlyDefault:0x0

Page 497 - Chapter 13

14-24 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414CTS: Clear To Send status. This bit is the

Page 498 - 13-2 DS785UM1

DS785UM1 14-25Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414UART1DMACtrl Address:0x808C_0028 - Read/Wr

Page 499 - 13.3 Address Pin Usage

14-26 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414Default:0x0000_0000Definition:Modem Control

Page 500 - 13.4 SDRAM Initialization

DS785UM1 14-27Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414Definition:Modem Status RegisterBit Descri

Page 501 - Step Action Reason

DS785UM1 2-17Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide222Note: The shaded memory areas are dedicat

Page 502 - 13-6 DS785UM1

14-28 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414CMAS: Clock Master: 1 - Transmitter and/or

Page 503

DS785UM1 14-29Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414RILEN: Receive Information Lost Interrupt

Page 504 - 13.6 SDRAM Self Refresh

14-30 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414CRCZ: CRC zero seed0 - Seed CRC calculation

Page 505 - 1 0 0 0 0 nSDCS3

DS785UM1 14-31Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414Default:0x0000_0000Definition:HDLC Address

Page 506 - X 1 1 0 0 nSDCS0

14-32 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414Definition:HDLC Receive Information Buffer

Page 507

DS785UM1 14-33Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414Address:0x808C_021C - Read/WriteDefault:0x

Page 508 - DS785UM1 13-12

14-34 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414TBY: Transmitter Busy. (Read Only)0 - TX is

Page 509 - DS785UM1 13-13

DS785UM1 14-35Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414RFS: Receive FIFO Service request. (Read O

Page 510 - DS785UM1 13-14

14-36 DS785UM1Copyright 2007 Cirrus LogicUART1 With HDLC and Modem Control SignalsEP93xx User’s Guide141414

Page 511 - DS785UM1 13-15

DS785UM1 15-1Copyright 2007 Cirrus Logic 151515Chapter 1515UART2 15.1 IntroductionUART2 implements a UART interface identical to that of UART1. UART2

Page 512 - DS785UM1 13-16

2-18 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8000_0140 - 0x8000_017C M2M Channel 1 Re

Page 513 - 13.9 Registers

15-2 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515 Figure 15-1. IrDA SIR Encoder/decoder Block Diagram 15.2.1.1 IrDA SIR Transmit

Page 514 - GlConfig

DS785UM1 15-3Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515A start bit is detected when the decoder input is LOW.Regardless of being in no

Page 515 - DS785UM1 13-19

15-4 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515 15.2.2.1 System/diagnostic Loopback TestingIt is possible to perform loopback t

Page 516 - Default: 0x0000_0080

DS785UM1 15-5Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515 15.2.4 Enabling Infrared (Ir) Modes 15.3 UART2 Package DependencyUART2 uses pa

Page 517 - BootSts

15-6 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515Fuartclk <= 4 x FpclkIf the IrDA SIR functionality is required, UARTCLK must

Page 518 - SDRAMDevCfg[3:0]

DS785UM1 15-7Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515 15.4 RegistersRegister DescriptionsUART2Data Address:0x808D_0000 - Read/WriteD

Page 519

15-8 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515UART2RXSts Address:0x808D_0004 - Read/WriteDefault:0x0000_0000Definition:UART Re

Page 520 - 13-24 DS785UM1

DS785UM1 15-9Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515FE: Framing Error. When this bit is set to “1”, it indicates that the received

Page 521 - DS785UM1 13-25

15-10 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515FEN: FIFO Enable. 1 - Transmit and receive FIFO buffers are enabled (FIFO mode)

Page 522 - 1 - Width is 16-bits

DS785UM1 15-11Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515Definition:UART Line Control Register Middle.Bit Descriptions:RSVD: Reserved.

Page 523 - Chapter 14

DS785UM1 2-19Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8001_0090 RXDQBAdd MAC Receive Descript

Page 524 - 14.2.1.3 Register Block

15-12 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515UART2Ctrl Address:0x808D_0014 - Read/WriteDefault:0x0000_0000Definition:UART Co

Page 525

DS785UM1 15-13Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515SIRLP: SIR Low Power Mode. This bit selects the IrDA encoding mode. If this bi

Page 526 - 14-4 DS785UM1

15-14 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515RXFF: Receive FIFO Full. The meaning of this bit depends on the state of the FE

Page 527 - 14.2.2 UART Operation

DS785UM1 15-15Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515Default:0x0000_0000Definition:UART Interrupt Identification and Interrupt Clea

Page 528 - 14.2.2.2 Disabling the FIFOs

15-16 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515ILPDV: IrDA Low Power Divisor bits [7:0]. 8-bit low-power divisor value. These

Page 529 - 14.2.3 Interrupts

DS785UM1 15-17Copyright 2007 Cirrus Logic UART2EP93xx User’s Guide151515UART2TMR Address:0x808D_0084 - Read/WriteDefault:0x0000_0000Definition:UART SI

Page 530 - 14.4 HDLC

15-18 DS785UM1Copyright 2007 Cirrus LogicUART2EP93xx User’s Guide151515.

Page 531 - 14.4.2 Selecting HDLC Modes

DS785UM1 16-1Copyright 2007 Cirrus Logic 161616Chapter 1616UART3 With HDLC Encoder 16.1 IntroductionNote: This chapter applies only to the EP9307, EP9

Page 532

16-2 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616 16.2.2 Clocking RequirementsThere are two clocks, PCLK and UA

Page 533 - 14.4.4 HDLC Receive

DS785UM1 16-3Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616As another example, assume 230,400 baud (the maximum with a U

Page 534 - 14.4.6 Address Matching

2-20 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8002_0030 HcDoneHead USB Host Controlle

Page 535 - 14.4.7 Aborts

16-4 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616a 3-bit status (break, frame and parity) is pushed onto the 11

Page 536 - 14.4.8 DMA

DS785UM1 16-5Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616BE: Break Error. This bit is set to 1 if a break condition wa

Page 537 - 14.5.1 Clocking Requirements

16-6 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616• UART3LinCtrlMid write, UART3LinCtrlLow write and UART3LinCtr

Page 538 - 14-16 DS785UM1

DS785UM1 16-7Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616UART3LinCtrlMid Address:0x808E_000C - Read/WriteDefault:0x000

Page 539 - 14.1 Registers

16-8 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616BR: Baud Rate Divisor bits [7:0]. Least significant byte of ba

Page 540 - UART1RXSts

DS785UM1 16-9Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616UART3Flag Address:0x808E_0018 - Read/WriteDefault:0x0000_0000

Page 541 - UART1LinCtrlHigh

16-10 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616BUSY: UART Busy. If this bit is set to 1, the UART is busy tr

Page 542 - UART1LinCtrlMid

DS785UM1 16-11Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616TIS: Transmit Interrupt Status. This bit is set to 1 if the

Page 543 - UART1LinCtrlLow

16-12 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616Default:0x0000_0000Definition:UART3 DMA Control RegisterBit D

Page 544 - UART1Flag

DS785UM1 16-13Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide1616160: Must be written as “0”.UART3HDLCCtrl Address:0x808E_020C

Page 545

DS785UM1 2-21Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8003_006C CursorColor1 Cursor color ove

Page 546 - UART1IntIDIntClr

16-14 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616RXENC: Receive Encoding method. 1 - Use Manchester bit encodi

Page 547 - UART1ModemCtrl

DS785UM1 16-15Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616CRCApd: CRC pass through.0 - Do not pass received CRC to CPU

Page 548 - UART1ModemSts

16-16 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616UART3HDLCAddMtchVal Address:0x808E_0210 - Read/WriteDefault:0

Page 549 - UART1HDLCCtrl

DS785UM1 16-17Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616UART3HDLCRXInfoBuf Address:0x808E_0218 - Read/WriteDefault:0

Page 550 - 14-28 DS785UM1

16-18 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616UART3HDLCSts Address:0x808E_021C - Read/WriteDefault:0x0000_0

Page 551 - DS785UM1 14-29

DS785UM1 16-19Copyright 2007 Cirrus Logic UART3 With HDLC EncoderEP93xx User’s Guide161616RAB: Receiver Abort. (Read Only)0 - No abort has been detect

Page 552 - UART1HDLCAddMtchVal

16-20 DS785UM1Copyright 2007 Cirrus LogicUART3 With HDLC EncoderEP93xx User’s Guide161616TAB: Transmitted Frame Aborted. (Read/Write)Set “1” when a tr

Page 553 - UART1HDLCRXInfoBuf

DS785UM1 17-1Copyright 2007 Cirrus Logic 171717Chapter 1717IrDA 17.1 IntroductionThis module implements the physical layer of an infrared serial port

Page 554 - UART1HDLCSts

17-2 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717 17.3 Shared IrDA Interface FeatureThis section describes features common to the

Page 555 - DS785UM1 14-33

DS785UM1 17-3Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 17.3.2.1 General Configuration 17.3.2.1.1 Select Ir ModeThe IrEnable register

Page 556 - 14-34 DS785UM1

vi ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s Guide 7.4.8.6 FRAME_CNTx timing ...

Page 557 - DS785UM1 14-35

2-22 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8008_0008 SMCBCR2Bank config Register 2

Page 558 - 14-36 DS785UM1

17-4 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717 17.3.2.2.2 The Transmit ProcessThis section describes the transmission process

Page 559 - Chapter 15

DS785UM1 17-5Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 17.3.2.2.3 Sending Packets Which are Not a Multiple of 4 Bytes In LengthThe tr

Page 560 - 15-2 DS785UM1

17-6 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717Set up DMA Set up a DMA buffer (the buffer should be greater than twice the maxim

Page 561 - 15.2.2 IrDA SIR Operation

DS785UM1 17-7Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717The data word and flags are held in the 39-bit wide receiver FIFO. Reading an Ir

Page 562 - 15.2.3 IrDA Data Modulation

17-8 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717 17.3.3 Control Information BufferingThe ARM Core needs several items of informat

Page 563 - 15.3.1 Clocking Requirements

DS785UM1 17-9Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 Figure 17-1. RZ1/NRZ Bit Encoding Example 17.4.1.2 Frame FormatMIR uses a flag

Page 564 - 15-6 DS785UM1

17-10 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717 17.4.1.2.1 Address FieldThe 8 bit address field is used by a transmitter to ta

Page 565 - 15.4 Registers

DS785UM1 17-11Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 17.4.2 Functional DescriptionFollowing reset, the MIR is disabled. Reset also

Page 566 - UART2RXSts

17-12 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717receive buffer, ignores the remainder of the frame and begins to search for the

Page 567 - UART2LinCtrlHigh

DS785UM1 17-13Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 17.4.2.3 Transmit OperationImmediately after enabling the MIR for transmission

Page 568 - UART2LinCtrlMid

DS785UM1 2-23Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x800B_0008 VIC1RawIntr Raw interrupt sta

Page 569 - UART2LinCtrlLow

17-14 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717 17.5.1 Introduction 17.5.1.1 4PPM ModulationFour position pulse modulation (4PP

Page 570 - UART2Ctrl

DS785UM1 17-15Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 Figure 17-3. 4PPM Modulation Example 17.5.1.2 4.0 Mbps FIR Frame FormatWhen t

Page 571 - UART2Flag

17-16 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717The preamble, start and stop flags are a mixture of symbols which contain either

Page 572 - UART2IntIDIntClr

DS785UM1 17-17Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717signalled. The CRC computation logic is preset to all ones before reception/tra

Page 573 - UART2IrLowPwrCntr

17-18 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717 17.5.2.2 Receive OperationThe IrDA standard specifies that all transmission occ

Page 574 - UART2DMACtrl

DS785UM1 17-19Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717When a framing error is detected all subsequent data in the frame is discarded

Page 575 - UART2TMR

17-20 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717When unexpected frame termination is selected and an underrun occurs, the transm

Page 576 - 15-18 DS785UM1

DS785UM1 17-21Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 17.5.4 IrDA Integration Information 17.5.4.1 Enabling Infrared Modes 17.5.4.2

Page 577 - 16UART3 With HDLC Encoder

17-22 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717To allow sufficient time to write the received data to the receive FIFO, UARTCLK

Page 578 - 16.2.2 Clocking Requirements

DS785UM1 17-23Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717 17.6 RegistersRegister DescriptionsIrEnable Address:0x808B_0000 - Read/WriteDe

Page 579 - 16.3 Registers

2-24 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x800B_0FE8 VIC1PeriphID2 VIC Identificati

Page 580 - UART3RXSts

17-24 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717EN: Enable value:00 - No encoder selected01 - SIR, 0 to 0.1152Mbit/s data rate,

Page 581 - UART3LinCtrlHigh

DS785UM1 17-25Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717TXP: Transmit Polarity Control.0 - Encoded data is not inverted before being pa

Page 582

17-26 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717address of all ones are broadcast frames, and are always matched regardless of t

Page 583 - UART3LinCtrlLow

DS785UM1 17-27Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717WST: Width Status.00 - All four bytes in receive buffer are valid.01 - Least si

Page 584 - UART3Ctrl

17-28 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717Bit Descriptions:DATA: IrDA data word. Values written and sent to the transmit F

Page 585 - UART3Flag

DS785UM1 17-29Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717IrRIB Address:0x808B_0020 - Read OnlyDefault:0x0000_0000Definition:IrDA Receive

Page 586 - UART3IntIDIntClr

17-30 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717BRAB: Buffered Receiver Abort.0 - No abort was detected in the last frame.1 - Th

Page 587 - UART3DMACtrl

DS785UM1 17-31Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717DMAERR: RX DMA error handing enable. If 0, the RX DMA interface ignores error c

Page 588 - UART3ModemCtrl

17-32 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717MISR Address:0x808B_0080 - Read/WriteDefault:0x0000_0000Definition:MIR Status Re

Page 589 - UART3HDLCCtrl

DS785UM1 17-33Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717RFS: Receive buffer Service Request (read only).0 - Receive buffer is empty or

Page 590 - UART3 With HDLC Encoder

DS785UM1 2-25Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x800C_022C VIC2VectCntl11 Vector control

Page 591 - DS785UM1 16-15

17-34 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717RFC: RFC mask bit. When high, the MIR RFC status can generate an interrupt.RFS:

Page 592 - UART3HDLCAddMask

DS785UM1 17-35Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717FISR Address:0x808B_0180 - Read/WriteDefault:0x0000_0000Definition:FIR Status R

Page 593 - UART3HDLCRXInfoBuf

17-36 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717RFS: Receive buffer Service Request (read only).0 - Receive buffer is empty or t

Page 594 - UART3HDLCSts

DS785UM1 17-37Copyright 2007 Cirrus Logic IrDAEP93xx User’s Guide171717RFC: RFC mask bit. When high, the FIR RFC status can generate an interrupt.RFS:

Page 595 - DS785UM1 16-19

17-38 DS785UM1Copyright 2007 Cirrus LogicIrDAEP93xx User’s Guide171717

Page 596 - 16-20 DS785UM1

DS785UM1 18-1Copyright 2007 Cirrus Logic 181818Chapter 1818Timers 18.1 IntroductionThe timers are used to control timed events in the system. For exam

Page 597 - Chapter 17

18-2 DS785UM1Copyright 2007 Cirrus LogicTimersEP93xx User’s Guide181818 18.1.2.1 Free Running ModeIn free running mode, counters TC1 and TC2 will wrap

Page 598 - 17.3.1 Overview

DS785UM1 18-3Copyright 2007 Cirrus Logic TimersEP93xx User’s Guide181818Register DescriptionsTimer1Load, Timer2Load Address:Timer1 - 0x8081_0000 -

Page 599 - 17.3.2.2 Transmitting Data

18-4 DS785UM1Copyright 2007 Cirrus LogicTimersEP93xx User’s Guide181818Definition:The Load register contains the initial value of the timer and is als

Page 600 - 17-4 DS785UM1

DS785UM1 18-5Copyright 2007 Cirrus Logic TimersEP93xx User’s Guide181818Address:Timer3 - 0x8081_0084 - Read OnlyReset Value:0x0000_0000Definition:The

Page 601 - 8, and if there are three

2-26 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8082_003C I2STX2En TX2 Channel Enable N0

Page 602 - 17.3.2.3.4 Error Conditions

18-6 DS785UM1Copyright 2007 Cirrus LogicTimersEP93xx User’s Guide181818Timer1Control, Timer2Control, Timer3Control Address:Timer1 - 0x8081_0008 - R

Page 603 - 17.3.2.4 Special Conditions

DS785UM1 18-7Copyright 2007 Cirrus Logic TimersEP93xx User’s Guide181818Timer4ValueLowAddress:Timer4 - 0x8081_0060 - Read OnlyReset Value:0x0000_0000D

Page 604 - 17.4.1 Introduction

18-8 DS785UM1Copyright 2007 Cirrus LogicTimersEP93xx User’s Guide181818Bit Descriptions:RSVD: Reserved. Unknown during a Read operation. Enable: Read/

Page 605 - 17.4.1.2 Frame Format

DS785UM1 19-1Copyright 2007 Cirrus Logic 191919Chapter 1919Watchdog Timer 19.1 IntroductionThe Watchdog Timer provides a mechanism for generating a sy

Page 606 - 17.4.1.2.4 CRC Field

19-2 DS785UM1Copyright 2007 Cirrus LogicWatchdog TimerEP93xx User’s Guide191919 19.1.1 Watchdog ActivationThe Watchdog circuitry may be disabled via s

Page 607 - 17.4.2.2 Receive Operation

DS785UM1 19-3Copyright 2007 Cirrus Logic Watchdog TimerEP93xx User’s Guide191919Note: A software reset can reset the system without this register losi

Page 608 - 17-12 DS785UM1

19-4 DS785UM1Copyright 2007 Cirrus LogicWatchdog TimerEP93xx User’s Guide191919READ ONLY BIT FIELDSPLSDSN: Pulse Disable Not. The Watchdog internal PL

Page 609 - 17.4.2.3 Transmit Operation

DS785UM1 19-5Copyright 2007 Cirrus Logic Watchdog TimerEP93xx User’s Guide191919WDStatusAddress:0x8094_0004 - Read/WriteDefault:0x0000_0000Definition:

Page 610 - 17.5.1 Introduction

19-6 DS785UM1Copyright 2007 Cirrus LogicWatchdog TimerEP93xx User’s Guide191919

Page 611

DS785UM1 20-1Copyright 2007 Cirrus Logic 202020Chapter 2020Real Time Clock With Software Trim 20.1 IntroductionThe Real Time Clock (RTC) is a circuit

Page 612 - 17.5.1.2.4 CRC Field

DS785UM1 2-27Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8084_005C IntStsFGPIO Interrupt Status

Page 613 - DS785UM1 17-17

20-2 DS785UM1Copyright 2007 Cirrus LogicReal Time Clock With Software TrimEP93xx User’s Guide202020 20.1.1.1 Software CompensationThe 1 Hz clock is ge

Page 614 - 17.5.2.2 Receive Operation

DS785UM1 20-3Copyright 2007 Cirrus Logic Real Time Clock With Software TrimEP93xx User’s Guide202020 20.1.1.4 Example - Measured Value Split Into Inte

Page 615 - 17.5.2.3 Transmit Operation

20-4 DS785UM1Copyright 2007 Cirrus LogicReal Time Clock With Software TrimEP93xx User’s Guide202020 20.1.2 Reset ControlThe RTC block level reset oper

Page 616 - 17.5.3 IrDA Connectivity

DS785UM1 20-5Copyright 2007 Cirrus Logic Real Time Clock With Software TrimEP93xx User’s Guide202020RTCMatch Address:0x8092_0004 - Read/WriteDefault:0

Page 617

20-6 DS785UM1Copyright 2007 Cirrus LogicReal Time Clock With Software TrimEP93xx User’s Guide202020RTCLoad Address:0x8092_000C - Read/WriteDefault:0x0

Page 618

DS785UM1 20-7Copyright 2007 Cirrus Logic Real Time Clock With Software TrimEP93xx User’s Guide202020RTCSWComp Address:0x8092_0108 - Read/WriteDefault:

Page 619 - 17.6 Registers

20-8 DS785UM1Copyright 2007 Cirrus LogicReal Time Clock With Software TrimEP93xx User’s Guide202020

Page 620 - 17-24 DS785UM1

DS785UM1 21-1Copyright 2007 Cirrus Logic 212121Chapter 2121I2S Controller 21.1 IntroductionThe I2S controller is used to stream serial audio data betw

Page 621 - IrAdrMatchVal

21-2 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121The primary I2S port and the I2S clocks are multiplexed and can be assi

Page 622

DS785UM1 21-3Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121• Supports 16/24/32 bit word lengths.• Programmable left/right word cl

Page 623

2-28 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8088_0034 AC97ISR2 Interrupt Status N0x8

Page 624 - IrDataTail

21-4 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121these two words will occupy positions 0 and 1 in the FIFO. The FIFO now

Page 625

DS785UM1 21-5Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121The I2S transmit and receive channels should be disabled before change

Page 626 - IrDMACR

21-6 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121• Programmable first data bit position. that is, I2S or non-I2S format.

Page 627

DS785UM1 21-7Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121Descriptions” on page 448.) Note that both left and right sample regis

Page 628

21-8 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121order to generate a set of audio clocks, LRCK (word clock) and SCLK (bi

Page 629

DS785UM1 21-9Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121 21.5 I2S Bit Clock Rate Generation 21.5.1 Example of the Bit Cloc

Page 630

21-10 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121 Figure 21-2. Bit Clock Generation Example 21.5.2 Example of Rig

Page 631

DS785UM1 21-11Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121• TX2 FIFO empty.• TX underflow.The first three can have their interr

Page 632

21-12 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121 21.7 Registers 21.7.1 I2S TX RegistersTable 21-7 summarizes the regis

Page 633

DS785UM1 21-13Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121I2S TX Register Descriptions I2STX0Lft Address:0x8082_0010 - Re

Page 634 - 17-38 DS785UM1

DS785UM1 2-29Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x808B_0008 IrAdrMatchVal IrDA Address Ma

Page 635 - 18Timers

21-14 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121I2STX1Lft Address:0x8082_0018 - Read/WriteDefault:0x0000_0000Defini

Page 636 - 18.2 Registers

DS785UM1 21-15Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121I2STX2Lft Address:0x8082_0020 - Read/WriteDefault:0x0000_0000Defi

Page 637 - Timer3Load

21-16 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121I2STXLinCtrlData Address:0x8082_0028 - Read/WriteDefault:0x0000_000

Page 638 - Timer3Value

DS785UM1 21-17Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121Definition:Transmit Control RegisterBit Descriptions:RSVD: Reserved.

Page 639 - Timer3Clear

21-18 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121Default:0x0000_0000Definition:TX0 Channel EnableBit Descriptions:RSVD:

Page 640 - Timer3Control

DS785UM1 21-19Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121Definition:TX2 Channel EnableBit Descriptions:RSVD: Reserved. Unknown

Page 641 - Timer4ValueHigh

21-20 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide2121210x0000_0000Definition:Receive left data word for channel 0.Bit Descrip

Page 642

DS785UM1 21-21Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121I2SRX1Rt Address:0x8082_004C - Read OnlyDefault:0x0000_0000Definit

Page 643 - 19Watchdog Timer

21-22 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121I2SRX2Rt Address:0x8082_0054 - Read OnlyDefault:0x0000_0000Definitio

Page 644 - 19.1.4 Watchdog Status

DS785UM1 21-23Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121RXDIR: Receive data shift direction.0 - MSB first1 - LSB firstI2SRXCt

Page 645 - 19.1 Registers

2-30 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x808E_xxxxUART3 UART3 Control Registers0x

Page 646 - Watchdog Timer

21-24 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121Bit Descriptions:RSVD: Reserved. Unknown During Read. Must be written

Page 647 - WDStatus

DS785UM1 21-25Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121Bit Descriptions:RSVD: Reserved. Unknown During Read. Must be written

Page 648 - 19-6 DS785UM1

21-26 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121I2S Configuration and Status Register DescriptionsI2STXClkCfg Address:

Page 649 - Chapter 20

DS785UM1 21-27Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121i2s_mstr: Defines if the TX Audio clocks areslave or master.0 - slave

Page 650 - 20-2 DS785UM1

21-28 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121i2s_rx_bcr: RX bit clock rate.00 - I2SRXClkCfg[4] defines the bit cloc

Page 651 - 20.1.1.6 Real-Time Interrupt

DS785UM1 21-29Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121 21.7.4 I2S Global Status RegistersI2S Global Status RegistersI2SGlSt

Page 652 - 20.1.2 Reset Control

21-30 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121Tx1_overflow: when = 1, the tx1 FIFO is full and an attempt has been m

Page 653 - RTCMatch

DS785UM1 21-31Copyright 2007 Cirrus Logic I2S ControllerEP93xx User’s Guide212121rx2_fifo_empty: when = 1, FIFO is empty, otherwise not emptyrx2_fifo_

Page 654 - RTCCtrl

21-32 DS785UM1Copyright 2007 Cirrus LogicI2S ControllerEP93xx User’s Guide212121

Page 655 - RTCSWComp

DS785UM1 22-1Copyright 2007 Cirrus Logic 222222Chapter 2222AC’97 Controller 22.1 IntroductionThe AC’97 Controller includes a 5-pin serial interface to

Page 656 - 20-8 DS785UM1

DS785UM1 2-31Copyright 2007 Cirrus Logic ARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8091_000C PWM0Invert PWM0 Invert N0x809

Page 657 - S Controller

22-2 DS785UM1Copyright 2007 Cirrus LogicAC’97 ControllerEP93xx User’s Guide222222and all modem data are at the same sampling rate. If the external cod

Page 658

DS785UM1 22-3Copyright 2007 Cirrus Logic AC’97 ControllerEP93xx User’s Guide222222transmitted at 48 kHz, the external codec does not have Data Request

Page 659 - DS785UM1 21-3

22-4 DS785UM1Copyright 2007 Cirrus LogicAC’97 ControllerEP93xx User’s Guide222222 22.2.1.3 RTISThe receive timeout interrupt is asserted when the rece

Page 660 - 21-4 DS785UM1

DS785UM1 22-5Copyright 2007 Cirrus Logic AC’97 ControllerEP93xx User’s Guide222222 22.2.2.4 GPIOTXCOMPLETEThe transmit GPIOTXCOMPLETE interrupt is ass

Page 661 - S Receiver Channel Overview

22-6 DS785UM1Copyright 2007 Cirrus LogicAC’97 ControllerEP93xx User’s Guide222222Register DescriptionsAC97DRx 0x8088_0030 Read AC97RISR2 Raw interrup

Page 662 - 21.3.1 Receiver FIFO’s

DS785UM1 22-7Copyright 2007 Cirrus Logic AC’97 ControllerEP93xx User’s Guide222222Address:AC97DR1 - 0x8088_0000 - Read/WriteAC97DR2 - 0x8088_0020 - Re

Page 663 - S Master Clock Generation

22-8 DS785UM1Copyright 2007 Cirrus LogicAC’97 ControllerEP93xx User’s Guide222222Definition:Receive Control Registers. The AC97RXCR registers are read

Page 664

DS785UM1 22-9Copyright 2007 Cirrus Logic AC’97 ControllerEP93xx User’s Guide222222RSIZE: Determines how many bits to a data word. See Table 22-3 for d

Page 665 - S Bit Clock Rate Generation

22-10 DS785UM1Copyright 2007 Cirrus LogicAC’97 ControllerEP93xx User’s Guide222222AC97TXCRx Address:AC97TXCR1 - 0x8088_0008 - Read/WriteAC97TXCR2 - 0x

Page 666 - 21.6 Interrupts

DS785UM1 22-11Copyright 2007 Cirrus Logic AC’97 ControllerEP93xx User’s Guide222222CM: Compact mode enable. If the RSIZE value is either “00” or “11”

Page 667 - DS785UM1 21-11

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. viiEP93xx User’s Guide8.6.4 Block Copy Function...

Page 668 - S TX Registers

2-32 DS785UM1Copyright 2007 Cirrus LogicARM920T Core and Advanced High-Speed Bus (AHB)EP93xx User’s Guide2220x8095_0000 - 0x8FFF_FFFF ReservedTable 2-

Page 669 - I2STX0Rt

22-12 DS785UM1Copyright 2007 Cirrus LogicAC’97 ControllerEP93xx User’s Guide222222TX1: FIFO contains SLOT1 data (only use if sampling rate is 48 kHz).

Page 670 - I2STX1Rt

DS785UM1 22-13Copyright 2007 Cirrus Logic AC’97 ControllerEP93xx User’s Guide222222TXBUSY: TXBUSY is set when TEN = “1” AND there is data in the FIFO,

Page 671 - I2STX2Rt

22-14 DS785UM1Copyright 2007 Cirrus LogicAC’97 ControllerEP93xx User’s Guide222222RTIS: RX Timeout Interrupt Status - If this bit is set to “1”, the t

Page 672 - I2STXCtrl

DS785UM1 22-15Copyright 2007 Cirrus Logic AC’97 ControllerEP93xx User’s Guide222222AC97IEx Address:AC97IE1 - 0x8088_0018 - Read/WriteAC97IE2 - 0x8088_

Page 673 - I2STX0En

22-16 DS785UM1Copyright 2007 Cirrus LogicAC’97 ControllerEP93xx User’s Guide222222next available frame in SLOT1. As both the AC97S1Data and AC97S2Data

Page 674 - I2STX2En

DS785UM1 22-17Copyright 2007 Cirrus Logic AC’97 ControllerEP93xx User’s Guide222222codec, the AC97S2Data register must be written to before the AC97S1

Page 675 - S RX Registers

22-18 DS785UM1Copyright 2007 Cirrus LogicAC’97 ControllerEP93xx User’s Guide222222AC97RGIS Address:0x8088_008C - Read OnlyDefinition:Raw Global Interr

Page 676 - I2SRX1Lft

DS785UM1 22-19Copyright 2007 Cirrus Logic AC’97 ControllerEP93xx User’s Guide222222AC97GIS Address:0x8088_0090 - Read OnlyDefinition:Global Interrupt

Page 677 - I2SRX2Lft

22-20 DS785UM1Copyright 2007 Cirrus LogicAC’97 ControllerEP93xx User’s Guide222222AC97IM Address:0x8088_0094 - Read/WriteDefinition:Controller Inter

Page 678 - I2SRXLinCtrlData

DS785UM1 22-21Copyright 2007 Cirrus Logic AC’97 ControllerEP93xx User’s Guide222222Definition:End Of Interrupt Register. The AC’97 End Of Interrupt Re

Page 679 - I2SRXWrdLen

DS785UM1 3-1Copyright 2007 Cirrus Logic 333Chapter 33MaverickCrunch Co-Processor 3.1 IntroductionNote:This chapter applies only to the EP9302, EP9307

Page 680 - I2SRX1En

22-22 DS785UM1Copyright 2007 Cirrus LogicAC’97 ControllerEP93xx User’s Guide222222AC97ResetAddress:0x8088_00A0 - Read/WriteDefinition:Controller Reset

Page 681 - 21.7.3 I

DS785UM1 22-23Copyright 2007 Cirrus Logic AC’97 ControllerEP93xx User’s Guide222222AC97SYNC Address:0x8088_00A4 - Read/WriteDefinition:Sync Control Re

Page 682 - I2STXClkCfg

22-24 DS785UM1Copyright 2007 Cirrus LogicAC’97 ControllerEP93xx User’s Guide222222AC97GCIS Address:0x8088_00A8 - Read OnlyDefinition:Global Channel In

Page 683 - I2SRXClkCfg

DS785UM1 23-1Copyright 2007 Cirrus Logic 232323Chapter 2323Synchronous Serial Port 23.1 IntroductionThe Synchronous Serial Port (SSP) is a master or s

Page 684 - 21-28 DS785UM1

23-2 DS785UM1Copyright 2007 Cirrus LogicSynchronous Serial PortEP93xx User’s Guide232323 23.3 SSP FunctionalityThe SSP includes a programmable bit rat

Page 685 - S Global Status Registers

DS785UM1 23-3Copyright 2007 Cirrus Logic Synchronous Serial PortEP93xx User’s Guide232323 23.5.2 Master/Slave ModeTo configure the SSP as a master, cl

Page 686 - 21-30 DS785UM1

23-4 DS785UM1Copyright 2007 Cirrus LogicSynchronous Serial PortEP93xx User’s Guide232323 23.5.5 Texas Instruments® Synchronous Serial Frame FormatFigu

Page 687 - I2SGlCtrl

DS785UM1 23-5Copyright 2007 Cirrus Logic Synchronous Serial PortEP93xx User’s Guide232323 23.5.6 Motorola® SPI Frame FormatThe Motorola SPI interface

Page 688 - 21-32 DS785UM1

23-6 DS785UM1Copyright 2007 Cirrus LogicSynchronous Serial PortEP93xx User’s Guide232323 Figure 23-4. Motorola SPI Frame Format (Continuous Transfer)

Page 689 - 22AC’97 Controller

DS785UM1 23-7Copyright 2007 Cirrus Logic Synchronous Serial PortEP93xx User’s Guide232323 23.5.8 Motorola SPI Format with SPO=0, SPH=1The transfer si

Page 690 - AC’97 Controller

3-2 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333• IEEE-754 single precision floating point (24-bit signed sig

Page 691 - 22.2.1 Channel Interrupts

23-8 DS785UM1Copyright 2007 Cirrus LogicSynchronous Serial PortEP93xx User’s Guide232323 23.5.9 Motorola SPI Format with SPO=1, SPH=0Single and contin

Page 692 - 22.2.2 Global Interrupts

DS785UM1 23-9Copyright 2007 Cirrus Logic Synchronous Serial PortEP93xx User’s Guide232323If the SSP is enabled and there is valid data within the tran

Page 693 - 22.4 Registers

23-10 DS785UM1Copyright 2007 Cirrus LogicSynchronous Serial PortEP93xx User’s Guide232323• when the SSP is configured as a master, the SSPCTLOE line i

Page 694 - Address Type Name Description

DS785UM1 23-11Copyright 2007 Cirrus Logic Synchronous Serial PortEP93xx User’s Guide232323Microwire format is very similar to SPI format, except that

Page 695 - AC97RXCRx

23-12 DS785UM1Copyright 2007 Cirrus LogicSynchronous Serial PortEP93xx User’s Guide232323 Figure 23-10. Microwire Frame Format (Continuous Transfers)

Page 696

DS785UM1 23-13Copyright 2007 Cirrus Logic Synchronous Serial PortEP93xx User’s Guide232323 23.6 RegistersThe SSP registers are shown in the following

Page 697 - CM RSIZE Data to CPU

23-14 DS785UM1Copyright 2007 Cirrus LogicSynchronous Serial PortEP93xx User’s Guide232323SCR: Serial clock rate. The value SCR is used to generate the

Page 698 - AC97TXCRx

DS785UM1 23-15Copyright 2007 Cirrus Logic Synchronous Serial PortEP93xx User’s Guide232323Default:0x0000_0000Definition:SSPCR1 is the control register

Page 699 - DS785UM1 22-11

23-16 DS785UM1Copyright 2007 Cirrus LogicSynchronous Serial PortEP93xx User’s Guide232323RIE: Receive FIFO interrupt enable:0 - Receive FIFO half-full

Page 700 - AC97SRx

DS785UM1 23-17Copyright 2007 Cirrus Logic Synchronous Serial PortEP93xx User’s Guide232323DATA: Transmit / Receive FIFO:Read - Receive FIFOWrite - Tra

Page 701 - AC97RISRx

DS785UM1 3-3Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333• InexactNote that the division by zero exception is not supp

Page 702 - AC97ISRx

23-18 DS785UM1Copyright 2007 Cirrus LogicSynchronous Serial PortEP93xx User’s Guide232323SSPCPSR Address:0x808A_0010 - Read/WriteDefault:0x0000_0000De

Page 703 - AC97S1Data

DS785UM1 23-19Copyright 2007 Cirrus Logic Synchronous Serial PortEP93xx User’s Guide232323Definition:The interrupt status is read from the SSP interru

Page 704 - AC97S2Data

23-20 DS785UM1Copyright 2007 Cirrus LogicSynchronous Serial PortEP93xx User’s Guide232323

Page 705 - AC97S12Data

DS785UM1 24-1Copyright 2007 Cirrus Logic 242424Chapter 2424Pulse Width Modulator 24.1 IntroductionNote: The EP9307 processor has one PWM with one outp

Page 706 - AC97RGIS

24-2 DS785UM1Copyright 2007 Cirrus LogicPulse Width ModulatorEP93xx User’s Guide242424With those two counters specified, a fixed pulse is generated. T

Page 707 - AC97GIS

DS785UM1 24-3Copyright 2007 Cirrus Logic Pulse Width ModulatorEP93xx User’s Guide242424 24.2.1.3 Dynamic Programming (PWM is Running) ExampleNote: Upd

Page 708 - AC97IM

24-4 DS785UM1Copyright 2007 Cirrus LogicPulse Width ModulatorEP93xx User’s Guide242424Note: All undefined register bits will be read as 0.Register Des

Page 709 - AC97GCR

DS785UM1 24-5Copyright 2007 Cirrus Logic Pulse Width ModulatorEP93xx User’s Guide242424Bit Descriptions:PWM_DC: PWM_DC is used in conjunction with PWM

Page 710 - AC97Reset

24-6 DS785UM1Copyright 2007 Cirrus LogicPulse Width ModulatorEP93xx User’s Guide242424Default:0x0000_0000Definition:PWMx InvertBit Descriptions:RSVD:

Page 711 - AC97SYNC

DS785UM1 25-1Copyright 2007 Cirrus Logic 252525Chapter 2525Analog Touch Screen Interface 25.1 IntroductionNote: The EP9301 and EP9302 processors each

Page 712 - AC97GCIS

3-4 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333A double precision value requires all 64 bits: A 32-bit integ

Page 713 - 23Synchronous Serial Port

25-2 DS785UM1Copyright 2007 Cirrus LogicAnalog Touch Screen InterfaceEP93xx User’s Guide252525 Figure 25-1. Different Types of Touch Screens For 8- an

Page 714 - 23.5 Configuring the SSP

DS785UM1 25-3Copyright 2007 Cirrus Logic Analog Touch Screen InterfaceEP93xx User’s Guide252525For 8-wire touch screens, the SX and SY lines are used

Page 715 - 23.5.4 Frame Format

25-4 DS785UM1Copyright 2007 Cirrus LogicAnalog Touch Screen InterfaceEP93xx User’s Guide252525 25.2.1 Touch Screen Scanning: Four-wire and Eight-wire

Page 716 - 23.5.5 Texas Instruments

DS785UM1 25-5Copyright 2007 Cirrus Logic Analog Touch Screen InterfaceEP93xx User’s Guide252525array scanning and enable the state machine. In determi

Page 717 - SPI Frame Format

25-6 DS785UM1Copyright 2007 Cirrus LogicAnalog Touch Screen InterfaceEP93xx User’s Guide252525 Figure 25-3. 4-Wire Analog Resistive Interface Switchin

Page 718 - Synchronous Serial Port

DS785UM1 25-7Copyright 2007 Cirrus Logic Analog Touch Screen InterfaceEP93xx User’s Guide252525The algorithm begins by putting the touch screen into i

Page 719 - DS785UM1 23-7

25-8 DS785UM1Copyright 2007 Cirrus LogicAnalog Touch Screen InterfaceEP93xx User’s Guide252525The difference between this new X value and the last val

Page 720

DS785UM1 25-9Copyright 2007 Cirrus Logic Analog Touch Screen InterfaceEP93xx User’s Guide252525 Figure 25-4. Analog Resistive Touch Screen Scan Flow C

Page 721 - DS785UM1 23-9

25-10 DS785UM1Copyright 2007 Cirrus LogicAnalog Touch Screen InterfaceEP93xx User’s Guide252525The algorithm then would continue by discharging and de

Page 722 - Frame Format

DS785UM1 25-11Copyright 2007 Cirrus Logic Analog Touch Screen InterfaceEP93xx User’s Guide252525 Figure 25-5. 5-Wire Analog Resistive Interface Switch

Page 723 - DS785UM1 23-11

DS785UM1 3-5Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333With saturation enabled (the default), the maximum representa

Page 724 - 23-12 DS785UM1

25-12 DS785UM1Copyright 2007 Cirrus LogicAnalog Touch Screen InterfaceEP93xx User’s Guide252525 Figure 25-6. 5-Wire Feedback (7-Wire) Analog Resistive

Page 725 - 23.6 Registers

DS785UM1 25-13Copyright 2007 Cirrus Logic Analog Touch Screen InterfaceEP93xx User’s Guide252525The register values for TSDirect can be derived from t

Page 726

25-14 DS785UM1Copyright 2007 Cirrus LogicAnalog Touch Screen InterfaceEP93xx User’s Guide252525The register values for TSDirect can be derived from th

Page 727

DS785UM1 25-15Copyright 2007 Cirrus Logic Analog Touch Screen InterfaceEP93xx User’s Guide252525 25.2.5 Measuring Touch Screen ResistanceThe analog sw

Page 728

25-16 DS785UM1Copyright 2007 Cirrus LogicAnalog Touch Screen InterfaceEP93xx User’s Guide252525 25.2.6 Polled and Interrupt-Driven ModesThe ADC provid

Page 729 - DS785UM1 23-17

DS785UM1 25-17Copyright 2007 Cirrus Logic Analog Touch Screen InterfaceEP93xx User’s Guide252525 25.3 Registers Note: The touch screen controller bloc

Page 730 - SSPIIR / SSPICR

25-18 DS785UM1Copyright 2007 Cirrus LogicAnalog Touch Screen InterfaceEP93xx User’s Guide252525Mask:03FF_FFFFDefinition:Analog Touch screen Setup and

Page 731

DS785UM1 25-19Copyright 2007 Cirrus Logic Analog Touch Screen InterfaceEP93xx User’s Guide252525TSXYMaxMin Address:0x8090_0004Default:0x0000_0000Defin

Page 732 - 23-20 DS785UM1

25-20 DS785UM1Copyright 2007 Cirrus LogicAnalog Touch Screen InterfaceEP93xx User’s Guide252525Bit Descriptions:RSVD: Reserved. Unknown during read.S

Page 733 - 24Pulse Width Modulator

DS785UM1 25-21Copyright 2007 Cirrus Logic Analog Touch Screen InterfaceEP93xx User’s Guide252525SCTL: Analog switch control values for the touch cont

Page 734 - 24.2.1.1 Example

3-6 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide33372 bits wide. If the accumulator saturation mode is disabled

Page 735 - 24.2.2 Programming Rules

25-22 DS785UM1Copyright 2007 Cirrus LogicAnalog Touch Screen InterfaceEP93xx User’s Guide252525TSSetup2 Address:0x8090_0024Default:0x0000_0000Definiti

Page 736 - PWMxDutyCycle

DS785UM1 25-23Copyright 2007 Cirrus Logic Analog Touch Screen InterfaceEP93xx User’s Guide252525DEVINT: Deviation Interrupt. This is the deviation er

Page 737 - PWMxInvert

25-24 DS785UM1Copyright 2007 Cirrus LogicAnalog Touch Screen InterfaceEP93xx User’s Guide252525

Page 738

DS785UM1 26-1Copyright 2007 Cirrus Logic 262626Chapter 2626Keypad Interface 26.1 IntroductionNote: This chapter applies only to the EP9307, EP9312, an

Page 739 - Chapter 25

26-2 DS785UM1Copyright 2007 Cirrus LogicKeypad InterfaceEP93xx User’s Guide262626 26.2 Theory of OperationThe circuitry scans an array of up to 64 key

Page 740 - Analog Touch Screen Interface

DS785UM1 26-3Copyright 2007 Cirrus Logic Keypad InterfaceEP93xx User’s Guide262626 Figure 26-2. 8 x 8 Key Array Diagram 26.2.1 Apparent Key Detecti

Page 741

26-4 DS785UM1Copyright 2007 Cirrus LogicKeypad InterfaceEP93xx User’s Guide262626• No press for address 0x1B at (ROW3, COL3)The ignored addresses, 0x1

Page 742 - 25-4 DS785UM1

DS785UM1 26-5Copyright 2007 Cirrus Logic Keypad InterfaceEP93xx User’s Guide262626 26.2.2 Scan and DebounceProducts are scanned based on the KEY_SCAN

Page 743 - DS785UM1 25-5

26-6 DS785UM1Copyright 2007 Cirrus LogicKeypad InterfaceEP93xx User’s Guide262626 26.2.4 Low Power ModeThe key scanning block also supports a low powe

Page 744 - 25-6 DS785UM1

DS785UM1 26-7Copyright 2007 Cirrus Logic Keypad InterfaceEP93xx User’s Guide262626Address:0x808F_0000Default:0x0000_0000Definition:Key scan initializa

Page 745 - DS785UM1 25-7

DS785UM1 3-7Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333condition code field of any subsequent ARM instruction to gat

Page 746 - 25-8 DS785UM1

26-8 DS785UM1Copyright 2007 Cirrus LogicKeypad InterfaceEP93xx User’s Guide262626PRSCL: Row/Column counter pre-scaler load value. This value is used

Page 747 - DS785UM1 25-9

DS785UM1 27-1Copyright 2007 Cirrus Logic 272727Chapter 2727IDE Interface 27.1 IntroductionNote: This chapter applies only to the EP9312 and EP9315 pro

Page 748 - 25-10 DS785UM1

27-2 DS785UM1Copyright 2007 Cirrus LogicIDE InterfaceEP93xx User’s Guide272727 27.2.1 Diagrams and State Machines Figure 27-1. IDE Interface Signal Co

Page 749 - DS785UM1 25-11

DS785UM1 27-3Copyright 2007 Cirrus Logic IDE InterfaceEP93xx User’s Guide272727Note: NI = Not supported at this time. 27.2.2 PIO OperationsFor PIO ope

Page 750 - 25.2.3 Direct Operation

27-4 DS785UM1Copyright 2007 Cirrus LogicIDE InterfaceEP93xx User’s Guide272727For a Write Operation.1. Write out the register value.2. Delay as follow

Page 751 - 5 wire detect Press

DS785UM1 27-5Copyright 2007 Cirrus Logic IDE InterfaceEP93xx User’s Guide272727In a write operation, when the DMA controller writes to IDEMDMADataOut

Page 752 - SAMPLE VBAT

27-6 DS785UM1Copyright 2007 Cirrus LogicIDE InterfaceEP93xx User’s Guide272727Machine sees that the incoming versus outgoing data rate is out of balan

Page 753 - DS785UM1 25-15

DS785UM1 27-7Copyright 2007 Cirrus Logic IDE InterfaceEP93xx User’s Guide272727latching of the data. It is calculated that the cycle time of AHB clock

Page 754 - Signals Function

27-8 DS785UM1Copyright 2007 Cirrus LogicIDE InterfaceEP93xx User’s Guide272727Note: This is the number of wait states required by the IDE Controller t

Page 755 - 25.3 Registers

DS785UM1 27-9Copyright 2007 Cirrus Logic IDE InterfaceEP93xx User’s Guide272727 27.2.7.3.3 Ultra DMA Read from IDE ControllerFollow the wait-state nu

Page 756

3-8 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333 3.2 Programming ExamplesThe examples below show two algorit

Page 757 - TSXYResult

27-10 DS785UM1Copyright 2007 Cirrus LogicIDE InterfaceEP93xx User’s Guide272727For both PIO and MDMA modes, the actual throughput is limited by the AR

Page 758

DS785UM1 27-11Copyright 2007 Cirrus Logic IDE InterfaceEP93xx User’s Guide272727Bit Descriptions:RSVD: Reserved. Unknown during read, ignored during w

Page 759 - TSSWLock

27-12 DS785UM1Copyright 2007 Cirrus LogicIDE InterfaceEP93xx User’s Guide272727Note: At most, one of the above 3 bits should be set to 1 at any time.

Page 760 - TSSetup2

DS785UM1 27-13Copyright 2007 Cirrus Logic IDE InterfaceEP93xx User’s Guide272727Default:0x0000_0000Definition:IDE UDMA Configuration Register.Bit Desc

Page 761 - DS785UM1 25-23

27-14 DS785UM1Copyright 2007 Cirrus LogicIDE InterfaceEP93xx User’s Guide272727IDEDataIn Address:0x800A_0014 - Read OnlyDefault:0x0000_0000Definition:

Page 762 - 25-24 DS785UM1

DS785UM1 27-15Copyright 2007 Cirrus Logic IDE InterfaceEP93xx User’s Guide272727DMA controller. A write by the host during MDMA data-out operation wil

Page 763 - 26Keypad Interface

27-16 DS785UM1Copyright 2007 Cirrus LogicIDE InterfaceEP93xx User’s Guide272727addressed and written by the DMA controller. A write by the host during

Page 764 - 26.2 Theory of Operation

DS785UM1 27-17Copyright 2007 Cirrus Logic IDE InterfaceEP93xx User’s Guide272727Definition:In UDMA data-out and data-in operations, this register cont

Page 765 - Keypad Interface

27-18 DS785UM1Copyright 2007 Cirrus LogicIDE InterfaceEP93xx User’s Guide272727IDEUDMADebug Address:0x800A_002C - Read/WriteDefault:0x0000_0000Definit

Page 766 - 26-4 DS785UM1

DS785UM1 27-19Copyright 2007 Cirrus Logic IDE InterfaceEP93xx User’s Guide272727Bit Descriptions:RSVD: Reserved. Unknown during read, ignored during w

Page 767 - 26.2.3 Interrupt Generation

DS785UM1 3-9Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333 loop cfmul32 c0, c0, c3 ; c0 <= c0 * 5 c

Page 768 - 26.2.5 Three-key Reset

27-20 DS785UM1Copyright 2007 Cirrus LogicIDE InterfaceEP93xx User’s Guide272727

Page 769

DS785UM1 28-1Copyright 2007 Cirrus Logic 282828Chapter 2828GPIO Interface 28.1 IntroductionNote: The EP9301 and EP9302 processors each have 18 standar

Page 770 - KeyDiagnostic

28-2 DS785UM1Copyright 2007 Cirrus LogicGPIO InterfaceEP93xx User’s Guide282828 Figure 28-1. System Level GPIO Connectivity Port AEGPIO[7:0]MUX_IOOE

Page 771 - 27IDE Interface

DS785UM1 28-3Copyright 2007 Cirrus Logic GPIO InterfaceEP93xx User’s Guide282828 28.1.1 Memory MapThe GPIO base address is 0x8084_0000. All registers

Page 772

28-4 DS785UM1Copyright 2007 Cirrus LogicGPIO InterfaceEP93xx User’s Guide282828In order to stop any spurious interrupts that may occur during the prog

Page 773 - 27.2.2 PIO Operations

DS785UM1 28-5Copyright 2007 Cirrus Logic GPIO InterfaceEP93xx User’s Guide282828 Figure 28-3. Signal Connections Within the Enhanced GPIO Port Control

Page 774 - 27.2.3 MDMA Operations

28-6 DS785UM1Copyright 2007 Cirrus LogicGPIO InterfaceEP93xx User’s Guide282828 28.1.4 GPIO Pin MapAll GPIO signals are mapped to device pins. The Sys

Page 775 - 27.2.4 UDMA Operations

DS785UM1 28-7Copyright 2007 Cirrus Logic GPIO InterfaceEP93xx User’s Guide2828284. EEDAT is the EEPROM data pin.5. ROW[7:0] are the Key Matrix row pin

Page 776 - 27.2.6 UDMA Example

28-8 DS785UM1Copyright 2007 Cirrus LogicGPIO InterfaceEP93xx User’s Guide2828281. IDEDA[2:0], IDECS0n, IDECS1n, and DIORn are IDE control pins.2. VS2,

Page 777 - 27.2.7 DMA Request Latency

DS785UM1 28-9Copyright 2007 Cirrus Logic GPIO InterfaceEP93xx User’s Guide28282810. COL[7:0] are the Key Matrix column pins.Note: The various function

Page 778

viii ©Copyright 2007 Cirrus Logic, Inc. DS785UM1 EP93xx User’s GuideChapter 10. DMA Controller...

Page 779 - Mode MAX IDE Device Bandwidth

3-10 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333 cfldrs c3, [r2], #4 ; c3 = *filter++;

Page 780 - 27.3 Registers

28-10 DS785UM1Copyright 2007 Cirrus LogicGPIO InterfaceEP93xx User’s Guide2828281. A read from the data register returns the value of the GPIO module

Page 781

DS785UM1 28-11Copyright 2007 Cirrus Logic GPIO InterfaceEP93xx User’s Guide282828PADR: 0x8084_0000 - Read/WritePBDR: 0x8084_0004 - Read/WritePCDR: 0x8

Page 782 - IDEUDMAOp

28-12 DS785UM1Copyright 2007 Cirrus LogicGPIO InterfaceEP93xx User’s Guide282828PxDIR: Port x direction bits. GPIOxIntEn Address:GPIOAIntEn: 0x808

Page 783 - IDEDataOut

DS785UM1 28-13Copyright 2007 Cirrus Logic GPIO InterfaceEP93xx User’s Guide282828The INTTYPE1 register controls what type of INTERRUPT can occur on Po

Page 784 - IDEMDMADataOut

28-14 DS785UM1Copyright 2007 Cirrus LogicGPIO InterfaceEP93xx User’s Guide282828GPIOxEOI Address:GPIOAEOI: 0x8084_0098 - Write OnlyGPIOBEOI: 0x808

Page 785 - IDEUDMADataOut

DS785UM1 28-15Copyright 2007 Cirrus Logic GPIO InterfaceEP93xx User’s Guide282828Bit Descriptions:RSVD: Reserved. Unknown During Read. PxINTDB: Interr

Page 786 - IDEUDMASts

28-16 DS785UM1Copyright 2007 Cirrus LogicGPIO InterfaceEP93xx User’s Guide282828IntStsA: 0x8084_00A0 - Read OnlyIntStsB: 0x8084_00BC - Read OnlyIntSts

Page 787

DS785UM1 28-17Copyright 2007 Cirrus Logic GPIO InterfaceEP93xx User’s Guide282828Definition:EEPROM interface pin drive type control. Defines the drive

Page 788 - IDEUDMAWrBufSts

28-18 DS785UM1Copyright 2007 Cirrus LogicGPIO InterfaceEP93xx User’s Guide282828

Page 789 - IDEUDMARdBufSts

DS785UM1 29-1Copyright 2007 Cirrus Logic 292929Chapter 2929Security 29.1 IntroductionSecurity is a generalized architecture consisting of Boot ROM, la

Page 790 - 27-20 DS785UM1

DS785UM1 3-11Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333DAID: MaverickCrunch Architecture ID. This read-only value

Page 791 - 28GPIO Interface

29-2 DS785UM1Copyright 2007 Cirrus LogicSecurityEP93xx User’s Guide292929 29.4 RegistersThis section contains the detailed register descriptions for s

Page 792

DS785UM1 30-1Copyright 2007 Cirrus Logic 303030Chapter 3030GlossaryTable 30-1. Glossary Term DefinitionAC’97Serial Audio data transmission standardADC

Page 793 - 28.1.1 Memory Map

30-2 DS785UM1Copyright 2007 Cirrus LogicGlossaryEP93xx User’s Guide303030LEDLight Emitting DiodeMACMedia Access Controller - EthernetMIIMedia Independ

Page 794 - (Ports C, D, E, G, H)

DS785UM1 31-1Copyright 2007 Cirrus Logic EP93XX Register ListEP93xx User’s Guide313131Chapter 3131EP93XX Register ListTable 31-1 provides an alphabeti

Page 795 - 28.1.3 Reset

31-2 DS785UM1Copyright 2007 Cirrus LogicEP93XX Register ListEP93xx User’s Guide313131BlinkMask 7-63BlinkPattrn 7-64BlinkRate 7-63BLKDESTHEIGHT 8

Page 796 - 28.1.4 GPIO Pin Map

DS785UM1 31-3Copyright 2007 Cirrus Logic EP93XX Register ListEP93xx User’s Guide313131DeviceCfg 5-25DiagAd 9-48DiagDa 9-49DMAChArb 10-45DMAG

Page 797

31-4 DS785UM1Copyright 2007 Cirrus LogicEP93XX Register ListEP93xx User’s Guide313131HcDoneHead 11-24HcFmInterval 11-24HcFmNumber 11-26HcFmRemaini

Page 798

DS785UM1 31-5Copyright 2007 Cirrus Logic EP93XX Register ListEP93xx User’s Guide313131I2STX0En 21-17I2STX0Lft 21-13I2STX0Rt 21-13I2ST

Page 799 - 28.2 Registers

31-6 DS785UM1Copyright 2007 Cirrus LogicEP93XX Register ListEP93xx User’s Guide313131IrDataTail 17-28IrDMACR 17-30IrEnable 17-23IrFlag 17-26Ir

Page 800

DS785UM1 31-7Copyright 2007 Cirrus Logic EP93XX Register ListEP93xx User’s Guide313131PWMxTermCnt 24-4PwrCnt 5-15PwrSts 5-14PxDDR 28-11P

Page 801 - PxDDR

3-12 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333SAT[1:0]: Accumulator saturation mode select. These bits are

Page 802 - GPIOxIntType1

31-8 DS785UM1Copyright 2007 Cirrus LogicEP93XX Register ListEP93xx User’s Guide313131RXStsThrshld 9-87SAR_BASEx 10-42SAR_CURRENTx 10-43ScratchRe

Page 803 - GPIOxIntType2

DS785UM1 31-9Copyright 2007 Cirrus Logic EP93XX Register ListEP93xx User’s Guide313131Timer3Control 18-6Timer3Load 18-3Timer3Value 18-4Ti

Page 804 - GPIOxDB

31-10 DS785UM1Copyright 2007 Cirrus LogicEP93XX Register ListEP93xx User’s Guide313131UART1HDLCCtrl 14-27UART1HDLCRXInfoBuf 14-31UART1HDLCSts 14

Page 805 - IntStsX

DS785UM1 31-11Copyright 2007 Cirrus Logic EP93XX Register ListEP93xx User’s Guide313131UART3RXSts 16-4USBCfgCtrl 11-36USBHCISts 11-37VActiveSt

Page 806 - EEDrive

31-12 DS785UM1Copyright 2007 Cirrus LogicEP93XX Register ListEP93xx User’s Guide313131VICxVectCntl11, 6-17VICxVectCntl12, 6-17VICxVectCntl13, 6-17VICx

Page 807

DS785UM1 3-13Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333UFE: Underflow Trap Enable. Enables/disables softwaretrappin

Page 808 - 28-18 DS785UM1

3-14 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333 3.4 ARM Co-Processor Instruction FormatThe ARM V4T archite

Page 809 - 29Security

DS785UM1 3-15Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Table 3-5 shows the condition codes, which are bits [31:28]

Page 810 - 29.4 Registers

3-16 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333co-processor uses this bit to distinguish between single pre

Page 811 - 30Glossary

DS785UM1 3-17Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333 3.5 Instruction Set for the MaverickCrunch Co-ProcessorTab

Page 812

3-18 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Fields that are ignored by the co-processor are shaded. Dark

Page 813 - 31EP93XX Register List

DS785UM1 3-19Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Moves from accumulatorCDPcfmv32al CRd, CRn Move accumulator

Page 814 - Register Name Page Number

DS785UM1 ©Copyright 2007 Cirrus Logic, Inc. ixEP93xx User’s Guide11.2.4 Host Controller Responsibilities...

Page 815 - DS785UM1 31-3

3-20 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Comparisons MRCcfcmps Rd, CRn, CRm Compare singles in CRn to

Page 816 - 31-4 DS785UM1

DS785UM1 3-21Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333 3.5.1 Load and Store InstructionsLoading Floating Point Va

Page 817 - DS785UM1 31-5

3-22 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Bit Definitions:N: Floating point precision - 0 for single,

Page 818 - 31-6 DS785UM1

DS785UM1 3-23Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Mnemonic: Bit Definitions:N: Floating point precision - 0 f

Page 819 - DS785UM1 31-7

3-24 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333 3.5.2 Move InstructionsMove Single Precision Floating Poin

Page 820 - 31-8 DS785UM1

DS785UM1 3-25Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Move Lower Half Double Precision Float from MaverickCrunch t

Page 821 - DS785UM1 31-9

3-26 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Move Lower Half 64-bit Integer from ARM to MaverickCrunchDes

Page 822 - 31-10 DS785UM1

DS785UM1 3-27Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Move Upper Half 64-bit Integer from MaverickCrunch to ARMDes

Page 823 - DS785UM1 31-11

3-28 DS785UM1Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Move MaverickCrunch Register to Middle AccumulatorDescriptio

Page 824 - 31-12 DS785UM1

DS785UM1 3-29Copyright 2007 Cirrus Logic MaverickCrunch Co-ProcessorEP93xx User’s Guide333Move High Accumulator to MaverickCrunch RegisterDescription:

Commentaires sur ces manuels

Pas de commentaire