Cirrus-logic EP7311 Manuel d'utilisateur télécharger pdf (Page 23)

DS506F2 Copyright Cirrus Logic, Inc. 2011

EP7311

High-Performance, Low-Power System on Chip

Static Memory Single Write Cycle

Note: 1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at

18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is

sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period

where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.

2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with

valid timing under zero wait state conditions.

3. Address, Data, Halfword, Word, and Write hold state until next cycle.

EXPCLK

nCS

nMWE

HALF-

WORD

WRITE

HWd

WDd

CSd

MWd

MWh

CSh

nMOE

EXPRDY

EXh

EXs

Figure 8. Static Memory Single Write Cycle Timing Measurement

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 41 42

Pas de commentaire

Cirrus-logic EP7311 Manuel d'utilisateur Page 23