Cirrus-logic EP7311 Manuel d'utilisateur télécharger pdf (Page 17)

DS506F2 Copyright Cirrus Logic, Inc. 2011

EP7311

High-Performance, Low-Power System on Chip

SDRAM Load Mode Register Cycle

Note: 1. Timings are shown with CAS latency = 2

2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.

Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal

SDCLK

SDCS

SDRAS

SDCAS

ADDR

DATA

SDQM

SDMWE

CSa

RAa

CAa

MWa

ADv

ADx

RAd

CSd

CAd

MWd

Figure 3. SDRAM Load Mode Register Cycle Timing Measurement

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 41 42

Pas de commentaire

Cirrus-logic EP7311 Manuel d'utilisateur Page 17