Cirrus-logic CS4362 Manuel d'utilisateur télécharger pdf (Page 11)

DS257F2 11

CS4362

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C

FORMAT

(For KQZ T

= -10°C to +70°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, C

=30pF)

Notes:

19. Data must be held for sufficient time to bridge the transition time, t

, of SCL.

20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

21. for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode.

Parameter Symbol Min Max Unit

SCL Clock Frequency f

scl

- 100 kHz

RST

Rising Edge to Start t

irs

500 - ns

Bus Free Time Between Transmissions t

buf

4.7 - µs

Start Condition Hold Time (prior to first clock pulse) t

hdst

4.0 - µs

Clock Low time t

low

4.7 - µs

Clock High Time t

high

4.0 - µs

Setup Time for Repeated Start Condition t

sust

4.7 - µs

SDA Hold Time from SCL Falling (Note 19) t

hdd

0-µs

SDA Setup time to SCL Rising t

sud

250 - ns

Rise Time of SCL and SDA t

, t

-1µs

Fall Time SCL and SDA t

, t

- 300 ns

Setup Time for Stop Condition t

susp

4.7 - µs

Acknowledge Delay from SCL Falling (Note 20) t

ack

- (Note 21) ns

256 Fs×

---------------------

128 Fs×

---------------------

64 Fs×

------------------

buf

hdst

low

hdd

high

sud

Stop Start

SDA

SCL

irs

RST

hdst

sust

susp

Start

Stop

Repeated

ack

Figure 3. Control Port Timing - I²C Format

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 41 42

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Cirrus-logic CS4362 Manuel d'utilisateur Page 11

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