Cirrus-logic CS8952 Manuel d'utilisateur Page 41
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CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 41
DS206F1
6.9 Interrupt Mask Register - Address 10h
This register indicates which events will cause an interrupt event on the MII_IRQ pin. Each bit acts as
an enable to the interrupt. Thus, when set, the event will cause the MII_IRQ
pin to be asserted. When
clear, the event will not affect the MII_IRQ
pin, but the status will still be reported via the Interrupt Sta-
tus Register (address 11h).
15 14 13 12 11 10 9 8
CIM Link
Unstable
Link Status
Change
Descrambler
Lock Change
Premature End
Error
DCR
Rollover
FCCR
Rollover
RECR
Rollover
Remote
Loopback
Fault
76543210
Reset
Complete
Jabber
Detect
Auto-Neg
Complete
Parallel
Detection Fault
Parallel
Fail
Remote
Fault
Page
Received
Reserved
BIT NAME TYPE RESET DESCRIPTION
15 CIM Link Unstable Read/Write 0 When set, an interrupt will be generated if an unsta-
ble link condition is detected by the Carrier Integrity
Monitor function.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
14 Link Status Change Read Write 1 When set, an interrupt will be generated each time
the CS8952 detects a change in the link status.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
13 Descrambler Lock
Change
Read/Write 0 When set, an interrupt will be generated each time
the 100BASE-TX receive descrambler loses or
regains synchronization with the far-end.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
12 Premature End
Error
Read/Write 0 When set, an interrupt will be generated when two
consecutive IDLES are detected in a 100BASE-TX
frame without the ESD sequence.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
- Features 1
- Description 1
- TABLE OF CONTENTS 2
- 10BASE-T CHARACTERISTICS 6
- 100BASE-X CHARACTERISTICS 7
- Start of 8
- 10BASE-T MII RECEIVE TIMING 12
- 10BASE-T MII TRANSMIT TIMING 13
- 3.1 Major Operating Modes 20
- 3.1.1.2 100 Mb/s Loopback 22
- 3.1.3.7 Carrier Detection 24
- 3.2 Auto-Negotiation 24
- 3.3 Reset Operation 25
- 3.4 LED Indicators 25
- 4.1 MII Frame Structure 26
- 4.2 MII Receive Data 26
- 4.3 MII Transmit Data 27
- 4.4 MII Management Interface 27
- 5. CONFIGURATION 29
- 5.3 Configuration via the MII 29
- 6. CS8952 REGISTERS 30
- 15 14 13 12 11 10 9 8 35
- 76543210 35
- Part Number Revision Number 36
- Disconnect Counter 47
- False Carrier Counter 48
- Scrambler Initialization Key 49
- Receive Error Counter 50
- 7. DESIGN CONSIDERATIONS 62
- 7.1 Twisted Pair Interface 62
- 7.2 100BASE-FX Interface 62
- 7.4 Clocking Schemes 63
- 7.5 Recommended Magnetics 64
- CS8952 100-pin 67
- (14 mm x 14 mm) 67
- 100L TQFP PACKAGE DRAWING 79
- 10.ORDERING INFORMATION 80
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