Cirrus-logic CS8420 Manuel d'utilisateur

Copyright © Cirrus Logic, Inc. 2007(All Rights Reserved)http://www.cirrus.comDigital Audio Sample Rate ConverterFeatures Complete IEC60958, AES3, S/P

10 DS245F4CS8420SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ MODEInputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.13. If Fso or Fsi is lower than 4

DS245F4 11CS8420SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® MODEInputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.16. Data must be held for suffici

12 DS245F4CS84202. TYPICAL CONNECTION DIAGRAMCS8420CableTerminationRXPRXNAES3/SPDIFSource3-wire SerialAudio SourceILRCKISCLKSDINClock Sourceand Contro

DS245F4 13CS84203. GENERAL DESCRIPTIONThe CS8420 is a fully asynchronous sample rate converter plus AES3 transceiver intended to be used in digital au

14 DS245F4CS84204. DATA I/O FLOW AND CLOCKING OPTIONSThe CS8420 can be configured for nine connectivity alternatives, referred to as data flows. Each

DS245F4 15CS8420The AESBP switch allows a TTL level, bi-phase mark-encoded data stream connected to RXP to be routed to theTXP and TXN pin drivers. Th

16 DS245F4CS8420Figure 8. Serial Audio Input, using PLL, SRC Enabled Figure 9. Serial Audio Input, No PLL, SRC EnabledSerialAudioInputAES3Encoder&am

DS245F4 17CS8420Figure 14. AES3 Input to Serial Audio Output, Serial Au-dio Input to AES3 Out, No SRCFigure 15. AES3 Input to Serial Audio Output On

18 DS245F4CS84205. SAMPLE RATE CONVERTER (SRC)Multirate digital signal processing techniques are used to conceptually upsample the incoming data to ve

DS245F4 19CS84206. THREE-WIRE SERIAL AUDIO PORTSA 3-wire serial audio input port and a 3-wire serial audio output port is provided. Each port can be a

2 DS245F4CS8420TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ...

20 DS245F4CS8420Figure 17. Serial Audio Input Example FormatsMSB LSBMSBLSBMSBILRCKISCLKSDINChannel A Channel BLeft Justified(In)ILRCKISCLKMSB LSBMSBL

DS245F4 21CS8420 Figure 18. Serial Audio Output Example FormatsX = don’t care to match format, but does need to be set to the desired setting* not

22 DS245F4CS84207. AES3 TRANSMITTER AND RECEIVERThe CS8420 includes an AES3-type digital audio receiver and an AES3-type digital audio transmitter. A

DS245F4 23CS84207.1.4 Channel Status Data HandlingThe first 2 bytes of the Channel Status block are decoded into the Receiver Channel Status register.

24 DS245F4CS84207.1.6 Non-Audio Auto DetectionSince it is possible to convey non-audio data in an AES3 data stream, it is important to know whether th

DS245F4 25CS84207.2.2 TXN and TXP DriversThe line drivers are low-skew, low-impedance, differential outputs capable of driving cables directly. Bothdr

26 DS245F4CS8420 Figure 20. AES3 Transmitter Timing for C, U and V Pin Input DataVCU[0] VCU[1] VCU[2] VCU[3] VCU[4]Data [4] Data [5] Data [6] Data [7

DS245F4 27CS8420 SRCAES3ReceiverAES3TransmitterPLLIn OutAA AABB BB96kHz stereo96kHz frame rate256x96kHz96kHz stereo96kHz frame rate96kHzFsi96kHzFsoOMC

28 DS245F4CS84208. AES3 TRANSMITTER AND RECEIVER8.1 Sample Rate ConverterThe equation for the group delay through the sample rate converter, with the

DS245F4 29CS84208.2 Non-SRC DelayThe unit of delay depends on the frame rate (sample rate) Fs. The AES receiver has a interface delay of twoframes. Th

DS245F4 3CS842010.13 Interrupt Register 2 Mode Registers MSB & LSB (0Dh,0Eh) ... 4210.14 Receive

30 DS245F4CS84209. CONTROL PORT DESCRIPTION AND TIMINGThe control port is used to access the registers, allowing the CS8420 to be configured for the d

DS245F4 31CS84209.2 I²C ModeIn I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, withthe clock t

32 DS245F4CS842010. CONTROL PORT REGISTER BIT DEFINITIONS10.1 Memory Address Pointer (MAP)This register defaults to 01INCR Auto-Increment Address Cont

DS245F4 33CS8420Addr(HEX)Function 7 6 5 4 3 2 1 001 Control 1SWCLK VSET MUTESAO MUTEAES DITH INT1 INT0 TCBLD02 Control 2TRUNC HOLD1 HOLD0 RMCKF MMR MM

34 DS245F4CS842010.2 Miscellaneous Control 1 (01h)SWCLK Causes OMCK to be output through the RMCK pin when the PLL is unlocked0 - RMCK is driven by th

DS245F4 35CS842010.3 Miscellaneous Control 2 (02h)TRUNC Determines whether the word length is set according to the incoming Channel Status data0 - Dat

36 DS245F4CS842010.4 Data Flow Control (03h)The Data Flow Control register configures the flow of audio data to/from the following blocks: Serial Audi

DS245F4 37CS842010.5 Clock Source Control (04h)This register configures the clock sources of various blocks. In conjunction with the Data Flow Control

38 DS245F4CS842010.6 Serial Audio Input Port Data Format (05h)SIMS Master/Slave Mode Selector0 - Serial audio input port is in Slave mode (default)1 -

DS245F4 39CS842010.7 Serial Audio Output Port Data Format (06h)SOMS Master/Slave Mode Selector0 - Serial audio output port is in Slave mode (default)1

4 DS245F4CS842016. PLL FILTER ...

40 DS245F4CS842010.8 Interrupt 1 Register Status (07h) (Read Only)For all bits in this register, a “1” means the associated interrupt condition has oc

DS245F4 41CS842010.9 Interrupt Register 2 Status (08h) (Read Only)For all bits in this register, a “1” means the associated interrupt condition has oc

42 DS245F4CS842010.12 Interrupt 2 Register Mask (0Ch)The bits of this register serve as a mask for the Interrupt 2 Register. If a mask bit is set to 1

DS245F4 43CS842010.14 Receiver Channel Status (0Fh) (Read Only)The bits in this register can be associated with either channel A or B of the received

44 DS245F4CS842010.15 Receiver Error (10h) (Read Only)This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occu

DS245F4 45CS842010.16 Receiver Error Mask (11h)The bits in this register serve as masks for the corresponding bits of the Receiver Error Regis-ter. If

46 DS245F4CS842010.18 User Data Buffer Control (13h)UD User data pin (U) direction specifier0 - The U pin is an input. The U data is latched in on bot

DS245F4 47CS842010.19 Sample Rate Ratio (1Eh) (Read Only)The Sample Rate Ratio is Fso divided by Fsi. This value is represented as an integer and a fr

48 DS245F4CS842011. SYSTEM AND APPLICATIONS ISSUES11.1 Reset, Power Down and Start-up OptionsWhen RST is low, the CS8420 enters a low-power mode. All

DS245F4 49CS842011.3 SRC Invalid StateOccasionally the CS8420 SRC will enter an invalid state. This can happen after the RUN bit has been setwhen an A

DS245F4 5CS8420Figure 35.Consumer Input Circuit ...

50 DS245F4CS842011.5 Block-Mode U-Data D-to-E Buffer Transfers When Fsi ≠ Fso, Block-Mode U-data transfers from the D buffer to the E buffer are not s

DS245F4 51CS842012. SOFTWARE MODE - PIN DESCRIPTIONThe above diagram and the following pin descriptions apply to Software mode. In Hardware mode, some

52 DS245F4CS8420FILT - PLL Loop Filter *An RC network should be connected between this pin and ground. Recommended schematic and component val-ues are

DS245F4 53CS8420EMPH - Pre-Emphasis Indicator OutputEMPH is low when the incoming AES3 data indicates the presence of 50/15 μs pre-emphasis. When the

54 DS245F4CS8420Miscellaneous Pins:U - User DataThe U pin may optionally be used to input User data for transmission by the AES3 transmitter (see Figu

DS245F4 55CS842013. HARDWARE MODES13.1 Overall DescriptionThe CS8420 has six Hardware modes, which allow use of the device without using a micro-contr

56 DS245F4CS842013.2 Hardware Mode 1 Description (DEFAULT Data Flow, AES3 Input)Hardware Mode 1 data flow is shown in Figure 24. Audio data is input v

DS245F4 57CS842013.2.1 Pin Description - Hardware Mode 1Overall Device Control:DFC0, DFC1 - Data Flow Control InputsDFC0 and DFC1 inputs determine the

58 DS245F4CS8420RERR - Receiver Error IndicatorWhen high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updat

DS245F4 59CS842013.3 Hardware Mode 2 Description(DEFAULT Data Flow, Serial Input)Hardware Mode 2 data flow is shown in Figure 25. Audio data is input

6 DS245F4CS84201. CHARACTERISTICS AND SPECIFICATIONSAll Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditi

60 DS245F4CS8420COPY/C ORIG/U Function00PRO=0, COPY=0, L=001PRO=0, COPY=0, L=110PRO=0, COPY=1, L=011PRO=1Table 9. HW Mode 2A COPY/C and ORIG/U Pin Fun

DS245F4 61CS842013.3.1 Pin Description - Hardware Mode 2Overall Device Control:DFC0, DFC1 - Data Flow Control InputsDFC0 and DFC1 inputs determine the

62 DS245F4CS8420RMCK - Input Section Recovered Master Clock OutputInput section recovered master clock output. Will be at a frequency of 256x the inpu

DS245F4 63CS842013.4 Hardware Mode 3 Description(Transceive Data Flow, with SRC)Hardware Mode 3 data flow is shown in Figure 26. Audio data is input v

64 DS245F4CS8420SDOUT RMCK RERR ORIG COPY FunctionLO - - - - Serial Output Port is SlaveHI - - - - Serial Output Port is Master- - - - LO Mode 3A: C t

DS245F4 65CS842013.4.1 Pin Description - Hardware Mode 3Overall Device Control:DFC0, DFC1 - Data Flow Control InputsDFC0 and DFC1 inputs determine the

66 DS245F4CS8420OLRCK - Serial Audio Output Port Left/Right Clock Input or OutputWord rate clock for the audio data on the SDOUT pin. The frequency wi

DS245F4 67CS842013.5 Hardware Mode 4 Description(Transceive Data Flow, No SRC) Hardware mode 4 data flow is shown in Figure 27. Audio data is input vi

68 DS245F4CS8420SDOUT RMCK RERR ORIG COPY FunctionLO - - - - Serial Output Port is SlaveHI - - - - Serial Output Port is Master- - - - LO Mode 4A: C t

DS245F4 69CS842013.5.1 Pin Description - Hardware Mode 4Overall Device Control:DFC0, DFC1 - Data Flow Control InputsDFC0 and DFC1 inputs determine the

DS245F4 7CS8420PERFORMANCE SPECIFICATIONS DIGITAL FILTER CHARACTERISTICS 2. See “AES3 Transmitter and Receiver” on page 28.DC ELECTRICAL SPECIFICATION

70 DS245F4CS8420OSCLK - Serial Audio Output Port Bit Clock Input or OutputSerial bit clock for audio data on the SDOUT pin.OLRCK - Serial Audio Output

DS245F4 71CS842013.6 Hardware Mode 5 Description (AES3 Receiver Only)Hardware Mode 5 data flow is shown in Figure 28. Audio data is input via the AES3

72 DS245F4CS842013.6.1 Pin Description - Hardware Mode 5Overall Device Control:DFC0, DFC1 - Data Flow Control InputsDFC0 and DFC1 inputs determine the

DS245F4 73CS8420AES3/SPDIF Receiver Interface:RXP, RXN - Differential Line Receiver InputsDifferential line receiver inputs, carrying AES3 type data.R

74 DS245F4CS842013.7 Hardware Mode 6 Description(AES3 Transmitter Only) Hardware Mode 6 data flow is shown in Figure 29. Audio data is input via the s

DS245F4 75CS8420Table 16. HW 6 Serial Port Format SelectionCOPY/C ORIG Function00PRO=0, COPY=0, L=001PRO=0, COPY=0, L=110PRO=0, COPY=1, L=011PRO=1Tabl

76 DS245F4CS842013.7.1 Pin Description - Hardware Mode 6Overall Device Control:DFC0, DFC1 - Data Flow Control InputsDFC0 and DFC1 inputs determine the

DS245F4 77CS8420ILRCK - Serial Audio Input Port Left/Right ClockInput or Output Word rate clock for the audio data on the SDIN pin. APMS - Serial Audi

78 DS245F4CS842014. EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPONENTS This section details the external components required to interfac

DS245F4 79CS8420The TXP pin may be used to drive TTL or CMOS gates as shown in Figure 32. This circuit may be used foroptical connectors for digital a

8 DS245F4CS8420DIGITAL INPUT CHARACTERISTICSDIGITAL INTERFACE SPECIFICATIONS AGND = DGND = 0 V; all voltages with respect to 0 V. TRANSMITTER CHARACTE

80 DS245F4CS8420connection. Generally, it may be a good idea to provide the option of grounding or capacitively coupling theshield to the chassis.In t

DS245F4 81CS842015. CHANNEL STATUS AND USER DATA BUFFER MANAGEMENTThe CS8420 has a comprehensive channel status (C) and user (U) data buffering scheme

82 DS245F4CS842015.1.1 Manually Accessing the E BufferThe user can monitor the data being transferred by reading the E buffer, which is mapped into th

DS245F4 83CS8420.15.1.2 Reserving the First 5 Bytes in the E BufferD-to-E buffer transfers periodically overwrite the data stored in the E buffer. Thi

84 DS245F4CS842015.1.5 One-Byte ModeIn many applications, the channel status blocks for the A and B channels will be identical. In this situation,if t

DS245F4 85CS8420transmitted bit. The first byte read is the first byte received, and the first byte sent is the first byte trans-mitted.15.2.3 IEC6095

86 DS245F4CS8420transmitter can read out data that had previously accumulated, allowing the FIFO to empty out. If the FIFObecomes completely empty, ze

DS245F4 87CS842016. PLL FILTER16.1 GeneralAn on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure41 is a

88 DS245F4CS842016.2.2 Capacitor SelectionThe type of capacitors used for the PLL filter can have a significant effect on receiver performance. Largeo

DS245F4 89CS842016.3.2 Locking to the RXP/RXN Receiver InputsCS8420 parts that are configured to lock to only the RXP/RXN receiver inputs should use t

DS245F4 9CS8420SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTSInputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.7. The active edges of ISCLK and OSCLK a

90 DS245F4CS842016.3.4 Jitter ToleranceShown in Figure 43 is the Receiver Jitter Tolerance template as illustrated in the AES3 and IEC60958-4specifica

DS245F4 91CS842017. PARAMETER DEFINITIONSInput Sample Rate (Fsi)The sample rate of the incoming digital audio.Input Frame RateThe frame rate of the re

92 DS245F4CS842018. PACKAGE DIMENSIONSTHERMAL CHARACTERISTICS AND SPECIFICATIONS INCHES MILLIMETERSDIM MIN MAX MIN MAXA 0.093 0.104 2.35 2.65A1 0.004

DS245F4 93CS842019. ORDERING INFORMATION20. REVISION HISTORY Product Description Package Pb-Free Grade Temp Range Container Order#CS8420Digital Audio

94 DS245F4CS8420Contacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one n