Cirrus-logic CS485xx Manuel d'utilisateur

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Copyright 2009 Cirrus Logic AUG ’09
DS734UM7
CS485xx
32-bit Audio DSP Family
http://www.cirrus.com
CS485xx
Hardware Users Manual
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Résumé du contenu

Page 1 - CS485xx

Copyright 2009 Cirrus Logic AUG ’09DS734UM7CS485xx 32-bit Audio DSP Familyhttp://www.cirrus.comCS485xx Hardware User’s Manual

Page 2

OverviewCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 1-2Figure 1-1 illustrates the functional block diagram for CS48560. F

Page 3 - Contents

Pin AssignmentsCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-2011 GPIO0 General Purpose Input/Output 3.3V (5V tol)BiDi IN

Page 4

9-21 Copyright 2009 Cirrus Logic, Inc. DS734UM7Revision HistoryCS485xx Hardware User’s Manual Revision History§§Revision Date ChangesUM1 December 06

Page 5

Revision HistoryCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-22

Page 6

1-3 Copyright 2009 Cirrus Logic, Inc. DS734UM7OverviewCS485xx Hardware User’s ManualFigure 1-2 illustrates the functional block diagram for CS48540. F

Page 7

OverviewCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 1-4Figure 1-3 illustrates the functional block diagram for CS48520. F

Page 8

1-5 Copyright 2009 Cirrus Logic, Inc. DS734UM7Code OverlaysCS485xx Hardware User’s ManualThis chip, teamed with Cirrus digital interface products and

Page 9 - 1.1 Overview

Functional Overview of the CS485xx ChipCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 1-6Table 1-1 lists the firmware availa

Page 10 - Overview

1-7 Copyright 2009 Cirrus Logic, Inc. DS734UM7Functional Overview of the CS485xx ChipCS485xx Hardware User’s Manualbuffers which are 32 bits wide. The

Page 11

Functional Overview of the CS485xx ChipCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 1-8 1.3.8 Serial Flash ControllerThe C

Page 12

1-9 Copyright 2009 Cirrus Logic, Inc. DS734UM7Functional Overview of the CS485xx ChipCS485xx Hardware User’s Manual 1.3.13 Programmable Interrupt Cont

Page 13 - 1.2 Code Overlays

Functional Overview of the CS485xx ChipCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 1-10

Page 14 - 1.3.2 Debug Controller (DBC)

2-1 Copyright 2009 Cirrus Logic, Inc. DS734UM7IntroductionCS485xxr Hardware User’s ManualChapter 2Operational Modes 2.1 IntroductionThe CS485xx has se

Page 15

DS734UM7 Copyright 2009 Cirrus Logic iiCS485xx Hardware User’s ManualContacting Cirrus Logic SupportFor all product questions and inquiries contact a

Page 16 - 1.3.9 DMA Controller

Operational Mode SelectionCS485xxr Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 2-2 2.2 Operational Mode SelectionThe operational

Page 17

2-3 Copyright 2009 Cirrus Logic, Inc. DS734UM7Slave Boot ProceduresCS485xxr Hardware User’s ManualPseudocode and flowcharts will be used to describe e

Page 18

Slave Boot ProceduresCS485xxr Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 2-4 Figure 2-2. Slave Boot SequenceMSG ==BOOT_STARTRESE

Page 19 - Introduction

2-5 Copyright 2009 Cirrus Logic, Inc. DS734UM7Slave Boot ProceduresCS485xxr Hardware User’s Manual 2.3.2.1 Slave Boot Procedure1. Toggle RESET. A down

Page 20 - 2.3 Slave Boot Procedures

Slave Boot ProceduresCS485xxr Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 2-6 2.3.3 Boot MessagesThe Slave Boot procedure uses a

Page 21 - 2.3.1 Slave Boot

2-7 Copyright 2009 Cirrus Logic, Inc. DS734UM7Master Boot ProcedureCS485xxr Hardware User’s ManualTable 2-5 is a quick reference showing the different

Page 22 - Slave Boot Procedures

SoftbootCS485xxr Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 2-8 2.5 SoftbootThe O/S application code for the CS485xx allows user

Page 23 - 2.3.2.1 Slave Boot Procedure

2-9 Copyright 2009 Cirrus Logic, Inc. DS734UM7SoftbootCS485xxr Hardware User’s Manual Figure 2-4. Soft Boot Sequence Flowchart 2.5.2.1 Softboot Steps1

Page 24 - 2.3.3 Boot Messages

SoftbootCS485xxr Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 2-10 Figure 2-5. Soft Boot Example Flowchart 2.5.2.2.1 Softboot Exam

Page 25

2-11 Copyright 2009 Cirrus Logic, Inc. DS734UM7SoftbootCS485xxr Hardware User’s Manual3. Read the SOFTBOOT_ACK message. If the message is the SOFTBOOT

Page 26 - 2.5 Softboot

DS734UM7 Copyright 2009 Cirrus Logic iiiContentsCS485xx Hardware User’s ManualContentsContents. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 27 - 2.5.2.2 Softboot Example

Low Power ModeCS485xxr Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 2-12 2.6 Low Power ModeThe CS485xx has a low power mode to ena

Page 28 - CS485xx to begin

2-13 Copyright 2009 Cirrus Logic, Inc. DS734UM7Low Power ModeCS485xxr Hardware User’s Manual Figure 2-6. Flowchart of Steps Used to Exit Low Power Mod

Page 29

Low Power ModeCS485xxr Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 2-140x§§Table 2-8. wakeup_uld Options and Values.uld Options V

Page 30 - Mnemonic Value

3-1 Copyright 2009 Cirrus Logic, Inc. DS734UM7IntroductionCS485xx Hardware User’s ManualChapter 3Serial Control Port 3.1 IntroductionThe CS485xx uses

Page 31 - Send .uld from Table 2

Serial Control Port ConfigurationCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-2 3.2.1 I2C PortThe CS485xx I2C bus has be

Page 32

3-3 Copyright 2009 Cirrus Logic, Inc. DS734UM7Serial Control Port ConfigurationCS485xx Hardware User’s Manual 3.2.2 I2C System Bus DescriptionDevices

Page 33 - 3.1 Introduction

Serial Control Port ConfigurationCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-4 3.2.2.1 I2C Bus DynamicsThe Start condit

Page 34 - 3.2.1 I

3-5 Copyright 2009 Cirrus Logic, Inc. DS734UM7Serial Control Port ConfigurationCS485xx Hardware User’s ManualThe number of bytes that can be transmitt

Page 35 - C System Bus Description

Serial Control Port ConfigurationCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-6 Figure 3-5. Data Byte with ACK and NACKA

Page 36 - C Bus Dynamics

3-7 Copyright 2009 Cirrus Logic, Inc. DS734UM7Serial Control Port ConfigurationCS485xx Hardware User’s Manual Figure 3-7. Repeated Start Condition wit

Page 37 - C Address with ACK and NACK

iv Copyright 2009 Cirrus Logic DS734UM7ContentsCS485xx Hardware User’s Manual 3.2.2.1 I2C Bus Dynamics...

Page 38

Serial Control Port ConfigurationCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-8 Figure 3-8. I2C Write Flow Diagram 3.2.2

Page 39 - 3.2.2.2.1 SCP_BSY Behavior

3-9 Copyright 2009 Cirrus Logic, Inc. DS734UM7Serial Control Port ConfigurationCS485xx Hardware User’s Manualafter each byte, the master must provide

Page 40 - C Write Protocol Procedure

Serial Control Port ConfigurationCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-10 Figure 3-9. I2C Read Flow DiagramSCP_IR

Page 41

3-11 Copyright 2009 Cirrus Logic, Inc. DS734UM7Serial Control Port ConfigurationCS485xx Hardware User’s Manual 3.2.2.4.1 I2C Read Protocol Procedure1.

Page 42 - C Read Flow Diagram

DS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-12Serial Control Port ConfigurationCS485xx Hardware User’s Manual Figure 3-10. Sample Waveform for I2C Wr

Page 43 - 3.2.2.4.2 SCP_IRQ Behavior

3-13 Copyright 2009 Cirrus Logic, Inc. DS734UM7SPI PortCS485xx Hardware User’s ManualIf there are more data words to read, IRQ will fall at the rising

Page 44 - M S S M S M S M S M M

3-14 Copyright 2009 Cirrus Logic, Inc. DS734UM7SPI PortCS485xx Hardware User’s Manual 3.3.1 SPI System Bus DescriptionThe SPI bus is a multi-master b

Page 45 - 3.3 SPI Port

3-15 Copyright 2009 Cirrus Logic, Inc. DS734UM7SPI PortCS485xx Hardware User’s ManualBoth modes of the CS485xx serial port are shown in Figure 3-13. F

Page 46

SPI PortCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-16 Figure 3-14. SPI Address and Data Bytes 3.3.1.1.1 SCP_BSY Behavi

Page 47 - 3.3.1.1 SPI Bus Dynamics

3-17 Copyright 2009 Cirrus Logic, Inc. DS734UM7SPI PortCS485xx Hardware User’s Manual 3.3.1.2 SPI MessagingMessaging to the CS485xx using the SPI bus

Page 48 - 3.3.1.1.1 SCP_BSY Behavior

DS734UM7 Copyright 2009 Cirrus Logic vFiguresCS485xx Hardware User’s Manual 8.2.1.2 Ground...

Page 49 - 3.3.1.2 SPI Messaging

SPI PortCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-18 Figure 3-15. SPI Write Flow Diagram 3.3.1.3.1 SPI Write Protocol

Page 50 - SPI Port

3-19 Copyright 2009 Cirrus Logic, Inc. DS734UM7SPI PortCS485xx Hardware User’s ManualWhen performing a SPI read, the same protocol is used whether rea

Page 51

SPI PortCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-205. If SCP_IRQ is still low after 4 bytes, then proceed to step 4

Page 52

DS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-21SPI PortCS485xx Hardware User’s Manual Figure 3-17. Sample Waveform for SPI Write Functional Timing Fig

Page 53

3-22 Copyright 2009 Cirrus Logic, Inc. DS734UM7SPI PortCS485xx Hardware User’s Manual 3.3.1.4.2 SCP_IRQ BehaviorThe SCP_IRQ signal is not part of the

Page 54

4-1 Copyright 2009 Cirrus Logic, Inc. DS734UM7IntroductionCS485xx Hardware User’s ManualChapter 4Digital Audio Input Interface 4.1 IntroductionCS485xx

Page 55

Digital Audio Input Port DescriptionCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 4-2 4.2.1 DAI Pin DescriptionTable 4-1 sh

Page 56 - 4.2.1 DAI Pin Description

4-3 Copyright 2009 Cirrus Logic, Inc. DS734UM7Digital Audio Input Port DescriptionCS485xx Hardware User’s Manual 4.2.2 Supported DAI Functional Blocks

Page 57 - DAI1_DATA2

Digital Audio Input Port DescriptionCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 4-4 Figure 4-3. 6-Channel DAI Port Block

Page 58

4-5 Copyright 2009 Cirrus Logic, Inc. DS734UM7Digital Audio Input Port DescriptionCS485xx Hardware User’s Manual Figure 4-4. 12-Channel DAI Port Block

Page 59 - 4.2.3 Digital Audio Formats

vi Copyright 2009 Cirrus Logic DS734UM7FiguresCS485xx Hardware User’s Manual Figure 3-18. Sample Waveform for SPI Read Functional Timing ...

Page 60 - C - LRCLK Polarity

DAI Hardware ConfigurationCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 4-6 Figure 4-5. I2S format (Rising Edge Valid SCLK)

Page 61 - H - Chip Version

4-7 Copyright 2009 Cirrus Logic, Inc. DS734UM7DAI Hardware ConfigurationCS485xx Hardware User’s ManualD - DAI Mode (Unsupported)E - DAI2_DATA Clock So

Page 62

DAI Hardware ConfigurationCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 4-8.Note: The.D Value, DAI Mode, is not supported o

Page 63

4-9 Copyright 2009 Cirrus Logic, Inc. DS734UM7DAI Hardware ConfigurationCS485xx Hardware User’s ManualTable 4-5. DAI2_DATA Clock Source (Input Paramet

Page 64 - DAI Hardware Configuration

DAI Hardware ConfigurationCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 4-10a. TDM (Time Division Multiplex) is only availa

Page 65 - Chapter 5

5-1 Copyright 2009 Cirrus Logic, Inc. DS734UM7Digital Audio Input Port DescriptionCS485xx Hardware User’s ManualChapter 5Direct Stream Data (DSD) Inpu

Page 66

Digital Audio Input Port DescriptionCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 5-2 Figure 5-1. DSD Port Block Diagram on

Page 67 - 6.1 Introduction

6-1 Copyright 2009 Cirrus Logic, Inc. DS734UM7IntroductionCS485xx Hardware User’s ManualChapter 6Digital Audio Output Interface 6.1 IntroductionThe CS

Page 68 - DAO_LRCLK

Digital Audio Output Port DescriptionCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 6-2DAO_MCLK is the master clock and is f

Page 69

6-3 Copyright 2009 Cirrus Logic, Inc. DS734UM7Digital Audio Output Port DescriptionCS485xx Hardware User’s Manual. Figure 6-2. CS48540 DAO Block Diagr

Page 70 - 6.2.3 DAO Interface Formats

DS734UM7 Copyright 2009 Cirrus Logic viiTablesCS485xx Hardware User’s ManualTablesTable 1-1. List of Available Firmware Modules and Associated Applica

Page 71

Digital Audio Output Port DescriptionCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 6-4 6.2.2 Supported DAO Functional Block

Page 72

6-5 Copyright 2009 Cirrus Logic, Inc. DS734UM7Digital Audio Output Port DescriptionCS485xx Hardware User’s Manual 6.2.3.3 One-line Data Mode Format (M

Page 73

Digital Audio Output Port DescriptionCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 6-6Please refer to Table 6-4, Table 6-5,

Page 74

6-7 Copyright 2009 Cirrus Logic, Inc. DS734UM7Digital Audio Output Port DescriptionCS485xx Hardware User’s Manual4DAO_MCLK = 128 FSDAO_SCLK = DAO_MCLK

Page 75 - 6.2.5 S/PDIF Transmitter

Digital Audio Output Port DescriptionCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 6-8Table 6-5 shows values and messages f

Page 76 - 0x00005080

6-9 Copyright 2009 Cirrus Logic, Inc. DS734UM7Digital Audio Output Port DescriptionCS485xx Hardware User’s ManualTable 6-6 shows values and messages f

Page 77 - 7.1 System Clocking Controls

Digital Audio Output Port DescriptionCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 6-10The DAO_DATA3/XMTA S/PDIF output pin

Page 78 - XTAL_OUT Divide-by-2

7-1 Copyright 2008 Cirrus Logic, Inc. DS734UM7System Clocking ControlsCS485xx Hardware User’s ManualChapter 7Crystal Oscillator and System Clocking 7.

Page 79 - 8.2 GPIO Description

Configuring the Crystal OscillatorCS485xx Hardware User’s ManualDS734UM7 Copyright 2008 Cirrus Logic, Inc. 7-2 Figure 7-1. Crystal Oscillator Schemati

Page 80 - Watchdog Timer Description

8-1 Copyright 2009 Cirrus Logic, Inc. DS734UM7IntroductionCS485xx Hardware User’s ManualChapter 8General Purpose Input/Output Pins 8.1 IntroductionThe

Page 81 - Typical Connection Diagrams

viii Copyright 2009 Cirrus Logic DS734UM7TablesCS485xx Hardware User’s ManualTable 8-5. PLL Filter Pins ...

Page 82

8-2 Copyright 2009 Cirrus Logic, Inc. DS734UM7Watchdog Timer DescriptionCS485xx Hardware User’s Manual 8.3 Watchdog Timer DescriptionAs mentioned earl

Page 83 - Figure 9-2. I

9-1 Copyright 2009 Cirrus Logic, Inc. DS734UM7Typical Connection DiagramsCS485xx Hardware User’s ManualChapter 8System Integration 9.1 Typical Connect

Page 84 - Figure 9-3. I

DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-2Typical Connection DiagramsCS485xx Hardware User’s Manual Figure 9-1. SPI Slave, 10 channels of Digital

Page 85 - Figure 9-4. I

DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-3Typical Connection DiagramsCS485xx Hardware User’s Manual Figure 9-2. I2C Slave, 10 Channels of Digital

Page 86

DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-4Typical Connection DiagramsCS485xx Hardware User’s Manual Figure 9-3. I2C Slave, 12 Channels of Digital

Page 87

DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-5Typical Connection DiagramsCS485xx Hardware User’s Manual Figure 9-4. I2C master, 10 Channels of Digital

Page 88

DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-6Typical Connection DiagramsCS485xx Hardware User’s Manual Figure 9-5. SPI Slave, 10 Channels of Digital

Page 89

DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-7Typical Connection DiagramsCS485xx Hardware User’s Manual Figure 9-6. SPI Slave, 10 Channels of Digital

Page 90 - 9.2 Pin Description

DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-8Typical Connection DiagramsCS485xx Hardware User’s Manual Figure 9-7. SPI Slave, 12 Channels of Digital

Page 91 - 9.2.2 PLL Filter

DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-9Typical Connection DiagramsCS485xx Hardware User’s Manual Figure 9-8. SPI Master, 10 Channels of Digital

Page 92 - 9.4 Control

1-1 Copyright 2009 Cirrus Logic, Inc. DS734UM7OverviewCS485xx Hardware User’s ManualChapter 1Introduction 1.1 OverviewThe CS485xx is a programmable au

Page 93 - 9.4.1 Operational Mode

Pin DescriptionCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-10 9.2 Pin Description 9.2.1 Power and GroundThe following s

Page 94 - 48-Pin LQFP Pin Assigments

9-11 Copyright 2009 Cirrus Logic, Inc. DS734UM7Pin DescriptionCS485xx Hardware User’s Manual 9.2.1.2 GroundFor two-layer circuit boards, care should b

Page 95

ClockingCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-12 9.2.3 PLLThe internal phase locked loop (PLL) of the CS485xx req

Page 96

9-13 Copyright 2009 Cirrus Logic, Inc. DS734UM7ControlCS485xx Hardware User’s Manual 9.4.1 Operational ModeThe control interface protocol used is dete

Page 97

48-Pin LQFP Pin AssigmentsCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-14 9.5 48-Pin LQFP Pin AssigmentsFigure 9-10 show

Page 98

9-15 Copyright 2009 Cirrus Logic, Inc. DS734UM748-Pin LQFP Pin AssigmentsCS485xx Hardware User’s ManualFigure 9-11 shows the 48-Pin LQFP Pin Layout of

Page 99

48-Pin LQFP Pin AssigmentsCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-16Figure 9-12 shows the 48-Pin LQFP Pin Layout of

Page 100 - Pin Assignments

9-17 Copyright 2009 Cirrus Logic, Inc. DS734UM7Pin AssignmentsCS485xx Hardware User’s Manual 9.6 Pin AssignmentsTable 9-9 shows the names and function

Page 101 - Revision Date Changes

Pin AssignmentsCS485xx Hardware User’s ManualDS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-18Table 9-10 shows the names and functions for each pin of t

Page 102 - Revision History

9-19 Copyright 2009 Cirrus Logic, Inc. DS734UM7Pin AssignmentsCS485xx Hardware User’s ManualTable 9-11 shows the names and functions for each pin of t

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