Cirrus-logic CS4353 Manuel d'utilisateur Page 1

Copyright  Cirrus Logic, Inc. 2011(All Rights Reserved)http://www.cirrus.com3.3 V Stereo Audio DAC with 2 VRMS Line OutputFeatures Multi-bit Delta-S

10 DS803F3CS4353DIGITAL INTERFACE CHARACTERISTICSTest conditions (unless otherwise specified): AGND = DGND = CPGND = 0 V; all voltages with respect to

DS803F3 11CS4353DC ELECTRICAL CHARACTERISTICSTest conditions (unless otherwise specified): VCP = VA = VL = 3.3 V; AGND = DGND = CPGND = 0 V; SDIN = 0;

12 DS803F3CS43533. TYPICAL CONNECTION DIAGRAMVL+0.9 V to +3.3 VRESETLRCKMCLKSCLKAOUT_REFSDINVFILT-AOUTAVA562 2.2 nFRextRextLine Level OutLeft & R

DS803F3 13CS43534. APPLICATIONS4.1 Line Outputs4.1.1 Ground-centered OutputsAn on-chip charge pump creates both positive and negative high-voltage sup

14 DS803F3CS43534.2 Sample Rate Range/Operational Mode DetectThe CS4353 operates in one of three operational modes. The device will auto-detect the co

DS803F3 15CS43534.4 Digital Interface FormatThe device will accept audio samples in either I²S or Left-Justified digital interface formats, as illustr

16 DS803F3CS43534.6 De-emphasis ControlThe device includes on-chip digital de-emphasis. Figure 7 shows the de-emphasis curve for Fs equal to44.1 kHz.

DS803F3 17CS43534.8 InitializationWhen power is first applied, the DAC enters a reset (low power) state at the beginning of the initializationsequence

18 DS803F3CS4353USER: Apply PowerUSER: Apply MCLKMCLK/LRCK Ratio DetectionUSER: Apply LRCK and SCLKReset StatePower-Down StateInitialization StatePowe

DS803F3 19CS43534.9 Recommended Power-up and Power-down Sequences4.9.1 Power-up Sequences4.9.1.1 External RESET Power-up SequenceFollow the power-up s

2 DS803F3CS4353TABLE OF CONTENTS1. PIN DESCRIPTIONS ...

20 DS803F3CS43532. Remove the MCLK signal without applying any glitched pulses to the MCLK pin.3. Remove the power supply voltages.Note: A glitched pu

DS803F3 21CS43535. DIGITAL FILTER RESPONSE PLOTS 0.4 0.5 0.6 0.7 0.8 0.9 1−120−100−80−60−40−200Frequency(normalized to Fs)Amplitude (dB)0.4 0.4

22 DS803F3CS43530.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55109876543210Frequency(normalized to Fs)Amplitude (dB)0 0.05 0.1 0.15 0.2 0.25 0.3

DS803F3 23CS43536. PARAMETER DEFINITIONSTotal Harmonic Distortion + Noise (THD+N)The ratio of the RMS value of the signal to the RMS sum of all other

24 DS803F3CS43537. PACKAGE DIMENSIONS Notes: 1. Dimensioning and tolerance per ASME Y 14.5M-1994.2. Dimensioning lead width applies to the metallized

DS803F3 25CS43538. ORDERING INFORMATION 9. REVISION HISTORY Release ChangesPP1– Updated interchannel isolation specification in the DAC Analog Charact

DS803F3 3CS4353LIST OF FIGURESFigure 1.Serial Input Timing ...

4 DS803F3CS43531. PIN DESCRIPTIONS Pin Name Pin # Pin DescriptionSCLK 1 Serial Clock (Input) - Serial clock for the serial audio interface.MCLK 2 Mas

DS803F3 5CS4353VA 17 Low Voltage Analog Power (Input) - Positive power supply for the analog section. VBIAS 18 Positive Voltage Reference (Output) - P

6 DS803F3CS43532. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONSAGND = DNGD = CPGND = 0 V; all voltages with respect to ground.No

DS803F3 7CS4353DAC ANALOG CHARACTERISTICSTest conditions (unless otherwise specified): TA = 25 °C; VCP = VA = 3.3 V; AOUT_REF = AGND = DGND = CPGND =

8 DS803F3CS43539. SDIN = 0. AOUT_REF input test signal is a 60 Hz, 50 mVpp sine wave. Measured by applying the testsignal into the AOUT_REF pin and me

DS803F3 9CS4353SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE Parameters Symbol Min Max UnitsMCLK Frequency 2.048 51.2 MHzMCLK Duty Cycle 45