Cirrus-logic CDB42448 Manuel d'utilisateur télécharger pdf (Page 18)

CDB42448

18 DS648DB2

5.2.4 SDIN1 MUX(SDINX.MUX)

Default = 10

Function:

This MUX selects the data lines from the CS8416, DSP Header, the ADC and the TDM Stream from

the TDMer (see Figure 4 on page 11).

5.3 CODEC CLOCK CONTROL (ADDRESS 03H)

5.3.1 DAC CLOCK MUX (DAC.CLK_MUX[1:0])

Default = 11

Function:

This MUX selects the sub-clock lines from the CS8416, ADC, DSP Header and the sub-clocks from

the TDMer internal to the FPGA (see Figure 3 on page 10).

5.3.2 FPGA CLOCKS TO DAC CLOCKS (FPGA->DAC

)

Default = 0

0 - FPGA Masters DAC clock bus

1 - FPGA Slave to DAC clock bus

Function:

This bit toggles a control line for the internal clock buffer to the DAC serial port (see Figure 3 on page

10) .

SDIN1.MUX[1:0] Data Selection

CS8416 SDOUT

DSP_ SDOUT1

ADC_SDOUT1

TDM Stream

Table 4. Data to SDIN1

76543210

Reserved Reserved DAC.CLK_

MUX1

DAC.CLK_

MUX0

FPGA->DAC ADC.CLK_

MUX1

ADC,CLK_

MUX0

FPGA->ADC-

CODEC

DAC.CLK_

MUX[1:0]

Clock Selection

CS8416

ADC

DSP DAC

TDMer

Table 5. Clocks to DAC

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 43 44

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Cirrus-logic CDB42448 Manuel d'utilisateur Page 18

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