Cirrus-logic CDB4245 Manuel d'utilisateur

Copyright © Cirrus Logic, Inc. 2005(All Rights Reserved)Cirrus Logic, Inc.www.cirrus.comCDB4245Evaluation Board for CS4245Featuresz Single-ended Analo

CDB424510 DS656DB14.4.2 SPDIF Recovered Clock - SPDIF to DAC & ADC to SPDIFUsing the pre-configured script file named “SPDIF Recovered Clock - SPD

CDB4245DS656DB1 115. FPGA REGISTER QUICK REFERENCEThis table shows the register names and their associated default values.Addr Function 7 6 5432 1 001

CDB424512 DS656DB16. FPGA REGISTER DESCRIPTION6.1 CODE REVISION ID - ADDRESS 01HFunction:Identifies the revision of the FPGA code. This register is Re

CDB4245DS656DB1 136.3 SUBCLOCK SOURCE CONTROL - ADDRESS 03H6.3.1 DAC SUBCLOCK SOURCE (BITS 5:4)Default = 01Function:These bits select the source of th

CDB424514 DS656DB16.4 CS4245 SDIN SOURCE CONTROL - ADDRESS 04H6.4.1 SDIN SOURCE (BITS 1:0)Default = 00Function:These bits select the source of the CS4

CDB4245DS656DB1 157. CDB CONNECTORS, JUMPERS, AND SWITCHES CONNECTORReference Designator INPUT/OUTPUT SIGNAL PRESENT+5V J1 Input+5.0 V Power Supp

CDB424516 DS656DB1 JUMPER PURPOSE POSITION FUNCTION SELECTEDJ3 Selects the source of voltage for the VLC supply.+1.8 V+2.5 V+3.3 V+5 V*Voltage source

CDB4245DS656DB1 178. CDB BLOCK DIAGRAM CS4245FPGACS8416 CS8406Passive Input FilterHeaderActive Input FilterHeaderMicrophone InputPassive Out

CDB424518 DS656DB19. CDB SCHEMATICS Figure 5. CS4245

CDB4245DS656DB1 19 Figure 6. Analog Inputs

CDB42452 DS656DB1TABLE OF CONTENTS1. SYSTEM OVERVIEW ...

CDB424520 DS656DB1 Figure 7. Analog Outputs

CDB4245DS656DB1 21 Figure 8. S/PDIF I/O

CDB424522 DS656DB1 Figure 9. Control Port

CDB4245DS656DB1 23 Figure 10. FPGA

CDB424524 DS656DB1 Figure 11. Discrete Clock Routing and Level Shifting

CDB4245DS656DB1 25 Figure 12. Power

CDB424526 DS656DB110.CDB LAYOUT Figure 13. Silk Screen

CDB4245DS656DB1 27 Figure 14. Topside Layer

CDB424528 DS656DB1 Figure 15. Bottom side Layer

CDB4245DS656DB1 2911.REVISION HISTORY Revision Date ChangesDB1 February 2005 Initial ReleaseTable 9. Revision HistoryContacting Cirrus Logic SupportFo

CDB4245DS656DB1 3LIST OF FIGURESFigure 1. CDB4245 Controls Tab...

CDB42454 DS656DB11. SYSTEM OVERVIEW The CDB4245 evaluation board is an excellent means for evaluating the CS4245 CODEC. Analog and digital audiosignal

CDB4245DS656DB1 51.6 FPGAThe FPGA handles both clock and data routing on the CDB4245. Clock and data routing selections madevia the CDB4245 Controls t

CDB42456 DS656DB11.12 USB Control PortThe USB control port connector (J37) is currently unavailable.2. SYSTEM CLOCKINGThe CDB4245 implements two discr

CDB4245DS656DB1 74. PC SOFTWARE CONTROLThe CDB4245 is shipped with a Microsoft Windows® based graphical user interface which allows control over theCS

CDB42458 DS656DB14.2 S/PDIF I/O Controls TabWhen the CDB4245 is configured to make use of the CS8416 S/PDIF receiver or CS8406 S/PDIF transmit-ter, th

CDB4245DS656DB1 94.3 Register Maps TabThe Register Maps tab provides low level control over the register level settings of the CS4245, CS8416,CS8406,