Cirrus-logic CS4207 Manuel d'utilisateur Page 133
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DS880F4 133
CS4207
1:0 Read/Write 10b
ADC1 SZCMode[1:0]: Sets the mode by which
analog PGA and digital volume, and muting
changes will be implemented. See “Input Ampli-
fier Capabilities” section on page 55 regarding
digital and analog volume ranges.
‘00’b - Immediate Change: When immediate
change is selected, all level changes will take
effect immediately in one step
‘01’b - Digital Immediate and Analog Zero Cross:
Dictates that signal level changes, both muting
and gain/attenuation, will occur immediately for
digital volume changes, and on a signal zero
crossing for analog volume changes to minimize
audible artifacts. The requested level change will
occur after a timeout period of 1024/Fs (approx.
21 ms @ Fs = 48 kHz) if the signal does not
encounter a zero crossing.
‘10’b - Digital Soft Ramp and Analog Soft Ramp:
Allows level changes, both muting and
gain/attenuation, to be implemented by incre-
mentally ramping at a rate of 1/8 dB per audio
sample period for digital volume changes, and at
a rate of 1 dB per 8 audio sample periods for
analog volume changes. If the analog PGA is
being used for +10 dB “boost” function, or the
Digital Mic is being used, then the digital soft
ramp gain range will be from +12 dB to -51 dB,
and analog soft ramp will not be used.
‘11’b - Digital Soft Ramp and Analog Zero Cross:
Allows level changes, both muting and
gain/attenuation, to be implemented by incre-
mentally ramping at a rate of 1/8 dB per audio
sample period for digital volume changes. Ana-
log volume changes are to be implemented on a
signal zero crossing. The requested level change
will occur after a timeout period of 1024/Fs
(approx. 21 ms @ Fs = 48 kHz) if the signal does
not encounter a zero crossing. If the analog PGA
is being used for +10 dB “boost” function, or the
Digital Mic is being used, then the digital soft
ramp gain range will be from +12 dB to -51 dB
and analog soft ramp will not be used.
Both soft ramp and zero cross are independently
monitored and implemented for each channel.
Bits Type Default Description
- DIGITAL to ANALOG FEATURES 1
- ANALOG to DIGITAL FEATURES 1
- System Features 2
- General Description 2
- TABLE OF CONTENTS 3
- LIST OF FIGURES 7
- LIST OF TABLES 7
- 1. PIN DESCRIPTIONS 8
- DS880F4 9 9
- Pin Name QFN Pin Description 9
- DS880F4 11 11
- 12 DS880F4 12
- ABSOLUTE MAXIMUM RATINGS 13
- (Note 4) 14
- 16 DS880F4 16
- (48 kHz Fs) 16
- LINEOUT_L/R 18
- HPOUT_L/R 20
- DS880F4 21 21
- Parameter Min Typ Max Unit 21
- Parameters Min Typ Max Units 21
- DMIC_SCL 22
- DMIC_SDA 22
- DS880F4 23 23
- POWER CONSUMPTION 24
- 4.1 Link Reset 25
- 4.2 Function Group Reset 25
- 4.3 Codec Initialization 25
- 26 DS880F4 26
- 28 DS880F4 28
- 5. PRESENCE DETECTION 31
- 32 DS880F4 32
- DS880F4 33 33
- 6.1.1 Node ID Summary 34
- DS880F4 35 35
- 6.2 Root Node (Node ID = 00h) 36
- 6.2.1 Vendor and Device ID 36
- 6.2.2 Revision ID 36
- 6.2.3 Subordinate Node Count 36
- 6.3.1 Subordinate Node Count 37
- 6.3.2 Function Group Type 37
- 38 DS880F4 38
- 6.3.6 Supported Power States 39
- 6.3.7 GPIO Capabilities 40
- 6.3.8 Power States 41
- 6.3.9 GPIO Data 42
- 6.3.10 GPIO Enable Mask 43
- 6.3.11 GPIO Direction 43
- 6.3.12 GPIO Sticky Mask 43
- 6.3.14 Function Reset 44
- DS880F4 45 45
- 46 DS880F4 46
- 6.4.4 Supported Power States 47
- 6.4.6 Power States 48
- 6.4.8 Converter Format 49
- 50 DS880F4 50
- 6.4.9 Amplifier Gain/Mute 51
- 52 DS880F4 52
- DS880F4 53 53
- 54 DS880F4 54
- 6.5.5 Connection List Length 55
- 6.5.6 Supported Power States 56
- DS880F4 57 57
- 6.5.11 Power States 58
- 6.5.13 Converter Format 59
- 60 DS880F4 60
- 6.5.14 Amplifier Gain/Mute 61
- 62 DS880F4 62
- DS880F4 63 63
- 64 DS880F4 64
- 6.6.4 Connection List Length 65
- 6.6.5 Supported Power States 65
- 6.6.6 Connection List Entry 65
- 6.6.7 Power States 66
- 6.6.9 Converter Format 67
- 68 DS880F4 68
- DS880F4 69 69
- 08h, 14h) 70
- DS880F4 71 71
- 6.7.4 Supported Power States 72
- 6.7.5 Power States 72
- DS880F4 73 73
- 6.7.7 Converter Format 74
- DS880F4 75 75
- 76 DS880F4 76
- DS880F4 77 77
- 6.8.2 Pin Capabilities 78
- 6.8.3 Connection List Length 79
- 6.8.4 Supported Power States 79
- 6.8.5 Connection List Entry 80
- 6.8.6 Power States 80
- 6.8.7 Pin Widget Control 81
- 82 DS880F4 82
- 6.8.9 Pin Sense 83
- 6.8.10 Configuration Default 83
- 84 DS880F4 84
- DS880F4 85 85
- 6.9.2 Pin Capabilities 86
- 6.9.3 Connection List Length 86
- 6.9.4 Supported Power States 87
- 6.9.5 Connection List Entry 87
- 6.9.6 Power States 87
- 6.9.7 Pin Widget Control 88
- DS880F4 89 89
- 6.9.9 Pin Sense 90
- 6.9.10 EAPD/BTL Enable 90
- 6.9.11 Configuration Default 91
- 92 DS880F4 92
- 6.10.2 Pin Capabilities 93
- 6.10.3 Connection List Length 93
- 6.10.4 Connection List Entry 94
- 6.10.5 Pin Widget Control 94
- 6.10.6 EAPD/BTL Enable 95
- 6.10.7 Configuration Default 96
- DS880F4 97 97
- 98 DS880F4 98
- 6.11.5 Supported Power States 99
- 6.11.6 Power States 99
- 100 DS880F4 100
- DS880F4 101 101
- 102 DS880F4 102
- 6.11.10 Pin Sense 103
- 104 DS880F4 104
- DS880F4 105 105
- 6.11.14 Amplifier Gain/Mute 106
- DS880F4 107 107
- 108 DS880F4 108
- 6.12.2 Pin Capabilities 109
- 6.12.4 Pin Widget Control 110
- DS880F4 111 111
- 6.12.7 Amplifier Gain/Mute 112
- DS880F4 113 113
- 114 DS880F4 114
- 6.13.2 Pin Capabilities 115
- 6.13.3 Supported Power States 115
- 6.13.4 Power States 116
- 6.13.5 Pin Widget Control 117
- 6.13.7 Pin Sense 118
- 6.13.8 Configuration Default 119
- 120 DS880F4 120
- 6.14.2 Pin Capabilities 121
- 6.14.3 Connection List Length 121
- 122 DS880F4 122
- 6.14.6 Pin Widget Control 123
- 124 DS880F4 124
- DS880F4 125 125
- 126 DS880F4 126
- 6.15.3 Processing State 127
- 6.15.4 Coefficient Index 127
- 6.15.5 Processing Coefficient 128
- 6.15.6 Coefficient Registers 128
- DS880F4 129 129
- 130 DS880F4 130
- DS880F4 131 131
- 132 DS880F4 132
- DS880F4 133 133
- 134 DS880F4 134
- DS880F4 135 135
- 136 DS880F4 136
- DS880F4 137 137
- 7. APPLICATIONS 138
- 7.2 Analog Inputs 139
- 140 DS880F4 140
- DS880F4 141 141
- 7.3 Analog Outputs 142
- 7.3.1 Output Filter 142
- 7.3.2 Analog Supply Removal 142
- 7.4 Digital Mic Inputs 142
- 7.5 S/PDIF Input and Outputs 143
- 7.5.1 S/PDIF Receiver SRC 143
- 8. PCB LAYOUT CONSIDERATIONS 144
- 9. PARAMETER DEFINITIONS 145
- 10.QFN PACKAGE DIMENSIONS 146
- THERMAL CHARACTERISTICS 146
- 11.ORDERING INFORMATION 147
- 12.REFERENCES 147
- 13.REVISION HISTORY 147
- 148 DS880F4 148
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