Cirrus-logic CDB42438 Manuel d'utilisateur télécharger pdf (Page 14)

CDB42438

14 DS646DB2

3.6 Bypass Control - Advanced

The DSP clocks and data may be routed through buffers directly to the CS42438, bypassing

the FPGA. This configuration may be desired for more stringent timing requirements at higher

clock speeds. See register “Bypass Control (address 06h)” on page 19. These bits are only

accessible through the Advanced tab of the Cirrus Logic FlexGui software.

Setting “Bypass_FPGA” to ‘0’b will route the DSP sub-clocks directly to the CODEC. “DSP-

DATA->DAC” and “SDOUT->DSP” should also be set to ‘0’b in bypass mode.

NOTE: To avoid contention with the FPGA, set the clock direction for the FPGA appropriately: The FPGA->CO-

DEC bits in register 03h must be set to ‘1’b.

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Cirrus-logic CDB42438 Manuel d'utilisateur Page 14