Cirrus-logic CS8406 Manuel d'utilisateur télécharger pdf (Page 19)

DS580F6 19

CS8406

8. CONTROL PORT REGISTER BIT DEFINITIONS

8.1 Memory Address Pointer (MAP)

Not a register

MAP[6:0] - Memory Address Pointer. Will automatically increment after each read or write.

8.2 Default = ‘000000’Control 1 (01h)

VSET - Transmitted Validity bit level

Default = ‘0’

0 - Indicates data is valid, linear PCM audio data

1 - Indicates data is invalid or not linear PCM audio data

MUTEAES - Mute control for the AES transmitter output

Default = ‘0’

0 - Not Muted

1 - Muted

INT1:0 - Interrupt output pin (INT) control

Default = ‘00’

00 - Active high; high output indicates interrupt condition has occurred

01 - Active low, low output indicates an interrupt condition has occurred

10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.

11 - Reserved

TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier

Default = ‘0’

0 - TCBL is an input

1 - TCBL is an output

8.3 Control 2 (02h)

MMT - Select AES3 transmitter mono or stereo operation

Default = ‘0’

0 - Normal stereo operation

1 - Output either left or right channel inputs into consecutive subframe outputs (Mono Mode, left or right is

determined by MMTLR bit)

76543210

0 MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0

76543210

0 VSET 0 MUTEAES 0 INT1 INT0 TCBLD

76543210

0 0 0 0 0 MMT MMTCS MMTLR

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 38 39

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Cirrus-logic CS8406 Manuel d'utilisateur Page 19