Cirrus-logic CS8427 Manuel d'utilisateur

1Copyright  Cirrus Logic, Inc. 2010(All Rights Reserved)www.cirrus.comCS842796 kHz Digital Audio Interface TransceiverFeatures Complete EIAJ CP1201,

CS842710 DS477F5SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE Note 17, Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.Notes: 17. I²C protocol

CS8427DS477F5 112. TYPICAL CONNECTION DIAGRAM* A separate analog supply is only necessary in applications where RMCK is usedfor a jitter sensitive tas

CS842712 DS477F53. GENERAL DESCRIPTIONThe CS8427 is an AES3 transceiver intended to beused in digital audio systems. Such systems in-clude digital mix

CS8427DS477F5 13Channel Status bits. The part also has a featurethat allows the first five bytes of Channel Statusmemory to be configured and transmit

CS842714 DS477F5clock routing and the associated control registerbits. The clock routing constraints determine whichdata routing options are actually

CS8427DS477F5 155. THREE-WIRE SERIAL AUDIO PORTSA 3-wire serial audio input port and a 3-wire serialaudio output port is provided. Each port can be ad

CS842716 DS477F56. AES3 RECEIVERThe CS8427 includes an AES3 digital audio re-ceiver and an AES3 digital audio transmitter. Acomprehensive buffering sc

CS8427DS477F5 17General on the incoming AES3 stream, copyrightwill always be indicated even when the stream in-dicates no copyright. Finally, the AUDI

CS842718 DS477F57. AES3 TRANSMITTERThe AES3 transmitter encodes and transmits au-dio and digital data according to the AES3,IEC60958 (S/PDIF), and EI

CS8427DS477F5 198. MONO MODE OPERATIONAn AES3 stream may be used in more than oneway to transmit 96-kHz sample rate data. Onemethod is to double the f

CS84272 DS477F5TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ... 5SPEC

CS842720 DS477F5SIMSPLLTXPTXNSDOUTOSCLKOLRCKOMCKRMCKRXPILRCKISCLKSDINMUXMUXMUXSWCLKUNLOCK010101CHANNELSTATUSMEMORYUSERBITMEMORYTRANSMITAES3SERIALAUDIO

CS8427DS477F5 21 AES3Encoder&DriverSerialAudioOutputOLRCKOSCLKSDOUTTXPTXNPLLRMCKTXD1-0:SPD1-0:OUTC:INC:RXD1-0:01101001Clock Source Control BitsDat

CS842722 DS477F5 VLRCKU (Out)VLRCK is a virtual word clock, which may not exist, but is used to illustrate the U timing.VLRCK duty cycle is 50%. VLRCK

CS8427DS477F5 23MSB LSBMSBLSBMSBILRCKISCLKSDINChannel A Channel BLeft Justified(In)ILRCKISCLKMSB LSBMSBLSBChannel ASDINMSBChannel BI²S(In)ILRCKISCLKCh

CS842724 DS477F5OLRCKOSCLKSDOUTChannel A Channel BLeft Justified(Out)OLRCKOSCLKChannel ASDOUTChannel BI²S(Out)OLRCKOSCLKChannel A Channel BMSBSDOUTMSB

CS8427DS477F5 259. CONTROL PORT DESCRIPTION AND TIMINGThe control port is used to access the registers, al-lowing the CS8427 to be configured for the

CS842726 DS477F5mode is used for active-low, wired-OR hook-upswith multiple peripherals connected to the micro-controller interrupt input pin.Many con

CS8427DS477F5 2710. CONTROL PORT REGISTER SUMMARY10.1 Memory Address Pointer (MAP)INCR - Auto Increment Address Control BitDefault = ‘0’0 - Disable1

CS842728 DS477F511. CONTROL PORT REGISTER BIT DEFINITIONS11.1 Control 1 (01h)SWCLK - Controls output of OMCK on RMCK when PLL loses lockDefault = ‘0’

CS8427DS477F5 29MMR - Select AES3 receiver mono or stereo operationDefault = ‘0’0 - Normal stereo operation1 - A and B subframes treated as consecutiv

CS8427DS477F5 311.14 Receiver Error (10h) (Read Only)... 3511.15 Receive

CS842730 DS477F5SPD1:SPD0 - Serial Audio Output Port Data SourceDefault = ‘10’00 - Reserved01 - Serial Audio Input Port10 - AES3 receiver11 - Reserved

CS8427DS477F5 3111.5 Serial Audio Input Port Data Format (05h)SIMS - Master/Slave Mode SelectorDefault = ‘0’0 - Serial audio input port is in slave m

CS842732 DS477F5SORES1:0 - Resolution of the output data on SDOUT and on the AES3 outputDefault = ‘00’ 00 - 24-bit resolution01 - 20-bit resolution10

CS8427DS477F5 3311.8 Interrupt 2 Status (08h) (Read Only)For all bits in this register, a “1” means the associated interrupt condition has occurred a

CS842734 DS477F511.11 Interrupt 2 Mask (0Ch)The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the er

CS8427DS477F5 35AUDIO - Audio indicator0 - Received data is linearly coded PCM audio1 - Received data is not linearly coded PCM audioCOPY - SCMS copyr

CS842736 DS477F511.15 Receiver Error Mask (11h)The bits in this register serve as masks for the corresponding bits of the Receiver Error register. If

CS8427DS477F5 3711.17 User Data Buffer Control (13h)UD - User data pin (U) direction specifier If this bit is changed during normal operation, then a

CS842738 DS477F511.19 OMCK/RMCK Ratio (1Eh) (Read Only)This register allows the calculation of the incoming sample rate by the host microcontroller f

CS8427DS477F5 3912. PIN DESCRIPTION - SOFTWARE MODESDA/CDOUTAD0/CSEMPHRXPRXNVA+AGNDFILTRSTRMCKRERRILRCKISCLKSDIN2827*26*25*24*23*22212019*18*17*16*151

CS84274 DS477F5LIST OF FIGURESFigure 1. Audio Port Master Mode Timing...

CS842740 DS477F5RERR 11 Receiver Error (Output) - When high, indicates an error condition from the AES3 receiver. The status of this pin is updated on

CS8427DS477F5 41TXPTXN2526Differential Line Driver (Output) - Drivers transmit AES3 data and are pulled low while the CS8427 is in the reset state.AD1

CS842742 DS477F513. HARDWARE MODE DESCRIPTIONHardware mode is selected by connecting the H/Spin to ‘1’. Hardware Mode data flow is shown inFigure 19.

CS8427DS477F5 43SDOUT RMCK RERR ORIG COPY FunctionLO - ---Serial Output Port is SlaveHI - ---Serial Output Port is Master----LOMode A: C transmitted d

CS842744 DS477F514. PIN DESCRIPTION - HARDWARE MODE* Pins which remain the same function in all modes.+ Pins which require a pull up or pull down resi

CS8427DS477F5 45ILRCK 12 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin.ISCLK 13 Serial Audio

CS842746 DS477F515. APPLICATIONS 15.1 Reset, Power Down and Start-up When RST is low, the CS8427 enters a low powermode and all internal states are re

CS8427DS477F5 4716. PACKAGE DIMENSIONSINCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA 0.093 0.098 0.104 2.35 2.50 2.65A1 0.004 0.008 0.012 0.10 0.20 0.

CS842748 DS477F5Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measu

CS8427DS477F5 4917. ORDERING INFORMATION Product Description Package Pb-Free Grade Temp Range Container Order #CS842796 kHz Digital Audio Interface T

CS8427DS477F5 51. CHARACTERISTICS AND SPECIFICATIONSAll Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditi

CS842750 DS477F518. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPONENTS This section details the external components re-quire

CS8427DS477F5 5118.3 AES3 Receiver External ComponentsThe CS8427 AES3 receiver is designed to acceptboth the professional and consumer interfaces.The

CS842752 DS477F519. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENTThe CS8427 has a comprehensive channel status(C) and user (U) data buffe

CS8427DS477F5 53For writing, the sequence starts after a E to F trans-fer, which is based on the output timebase. Sincea D to E transfer could occur a

CS842754 DS477F5When reading data in one byte mode, a single byteis returned, which can be from channel A or B data,depending on a register control bi

CS8427DS477F5 5520.APPENDIX C: PLL FILTER20.1 GeneralAn on-chip Phase Locked Loop (PLL) is used to re-cover the clock from the incoming data stream.Fi

CS842756 DS477F520.2 External Filter Components20.2.1 GeneralThe PLL behavior is affected by the external filtercomponent values. Figure 5 on page 11

CS8427DS477F5 5720.3 Component Value SelectionWhen transitioning from one revision of the partanother, component values may need to bechanged. While i

CS842758 DS477F520.3.3 Locking to the ILRCK InputCS8427 parts that are configured to lock to the IL-RCK input should use the external PLL componentval

CS8427DS477F5 5920.3.5 Jitter AttenuationShown in Figure 33, Figure 34, Figure 35, and Fig-ure 36 are jitter attenuation plots for the various re-visi

CS84276 DS477F5DC ELECTRICAL CHARACTERISTICS AGND = DGND = 0 V; all voltages with respect to 0 V. Notes: 3. Power Down Mode is defined as RST = LO w

CS842760 DS477F521. REVISION HISTORY Release Date ChangesPP1 November 1999 1st Preliminary ReleasePP2 November 2000 2nd Preliminary ReleasePP3 Ma

CS8427DS477F5 7SWITCHING CHARACTERISTICS Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF. Notes: 6. Cycle-to-cycle locking to RXP/RXN using 32 to 96

CS84278 DS477F5SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.Notes: 8. The active edges of ISCLK and

CS8427DS477F5 9SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.Notes: 14. If Fso or Fsi is lower