Cirrus-logic CDB8421 Manuel d'utilisateur

Copyright © Cirrus Logic, Inc. 2004(All Rights Reserved)Cirrus Logic, Inc.www.cirrus.comCDB8421Evaluation Board For CS8421Features Asynchronous Sampl

CDB842110 DS641DB3Figure 3. CS8416

CDB8421DS641DB3 11 Figure 4. CS8416 to CS8421

CDB842112 DS641DB3Figure 5. CS8421

CDB8421DS641DB3 13 Figure 6. CS8421 to CS8406

CDB842114 DS641DB3 Figure 7. CS8406

CDB8421DS641DB3 15Figure 8. Mode Switches

CDB842116 DS641DB3Figure 9. CPLD

CDB8421DS641DB3 174. LAYOUT Figure 10. Silk Screen

CDB842118 DS641DB3Figure 11. Topside Layer

CDB8421DS641DB3 19Figure 12. Bottomside Layer

CDB84212 DS641DB3TABLE OF CONTENTS1. SYSTEM OVERVIEW ...

CDB842120 DS641DB35. APPENDIX A: CS8406 TCBL CONNECTION FOR THE CDB8421 REV. APin 15 of U19 on the CDB8421 Rev. A has been lifted. This eliminates the

CDB8421DS641DB3 216. REFERENCES[1] CS8421 - 32-bit, 192 kHz, Asynchronous, Stereo Sample Rate Converter web page: http://www.cirrus.com/en/products

CDB842122 DS641DB37. REVISION HISTORY Release Date ChangesDB1 October 2004 1st ReleaseDB2 November 2004 Corrected figure caption on page 10.DB3 Nov

CDB8421DS641DB3 31. SYSTEM OVERVIEW The CDB8421 demonstration board is an excellent means for evaluating the CS8421 stereosample rate converter. Digit

CDB84214 DS641DB31.4 ClockingTable 1 shows the available I/O configurations and their respective clock sources. When theCS8416 is selected to master S

CDB8421DS641DB3 5Switch S2 controls the interface format of the CS8406 and the CS8421 output port. The func-tions for switches S2[3:0] are detailed in

CDB84216 DS641DB3Switch S4 allows any of the PCM clocks/data to be turned off, selection between the OPTI-CAL and COAXIAL S/PDIF inputs, bypassing the

CDB8421DS641DB3 7 CONNECTORReference Designator INPUT/OUTPUT SIGNAL PRESENT+5V J1 Input +5.0 V Power SupplyGND J2 Input Ground ReferenceVL J3 Input

CDB84218 DS641DB32. BLOCK DIAGRAMFigure 1. Block Diagram

CDB8421DS641DB3 93. SCHEMATICS Figure 2. Power