Cirrus-logic CS5490 Manuel d'utilisateur

Copyright  Cirrus Logic, Inc. 2013(All Rights Reserved)Cirrus Logic, Inc.http://www.cirrus.comCS5490Two Channel Energy Measurement ICFeatures• Superi

CS549010 DS982F3ANALOG CHARACTERISTICS• Min/Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• Typical

CS5490DS982F3 11Notes: 5. All outputs unloaded. All inputs CMOS level.6. Temperature accuracy measured after calibration is performed.7. Measurement m

CS549012 DS982F3DIGITAL CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• Typic

CS5490DS982F3 13SWITCHING CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• Typ

CS549014 DS982F3ABSOLUTE MAXIMUM RATINGSNotes: 15. VDDA and GNDA must satisfy [(VDDA) – (GNDA)]  + 4.0V.16. Applies to all pins, including continuous

CS5490DS982F3 154. SIGNAL FLOW DESCRIPTIONThe signal flow for voltage, current measurement, andthe other calculations is shown in Figure 6.The signal

CS549016 DS982F34.6 High-pass & Phase Matching FiltersOptional high-pass filters (HPF in Figure 6) remove anyDC component from the selected signa

CS5490DS982F3 17SampleCount register should not be changed from itsdefault value of 4000, and bit AFC of the Config2register must be set. During conti

CS549018 DS982F35. FUNCTIONAL DESCRIPTION5.1 Power-on Reset (POR)The CS5490 has an internal power supply supervisorcircuit that monitors the VDDA and

CS5490DS982F3 195.4 Line Frequency Measurement If the Automatic Frequency Calculation (AFC) bit in theConfig2 register is set, the line frequency mea

CS54902 DS982F3TABLE OF CONTENTS1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CS549020 DS982F3After reset, the energy pulse generation block isdisabled (DOMODE[3:0] = Hi-Z). To output a desiredenergy pulse to a DO pin, it is nec

CS5490DS982F3 21The CS5490 pulse generation block behaves asfollows: • The pulse rate generated by full-scale (1.0 decimal) power register isFOUT=(Pul

CS549022 DS982F35.7 Phase Sequence DetectionPolyphase meters using multiple CS5490 devices maybe configured to sense the succession of voltagezero-cr

CS5490DS982F3 235.8 Temperature MeasurementThe CS5490 has an internal temperature sensor, whichis designed to measure temperature and optionallycompe

CS549024 DS982F36. HOST COMMANDS AND REGISTERS6.1 Host CommandsThe first byte sent to the CS5490 RX pin contains thehost command. Four types of host

CS5490DS982F3 256.1.3 ChecksumTo improve the communication reliability on the serialinterface, the CS5490 provides a checksum mechanismon transmitted

CS549026 DS982F36.2 Hardware Registers Summary (Page 0)Address2RA[5:0] Name Description1DSP3HOST3Default0* 00 0000 Config0 Configuration 0 Y Y 0x C0

CS5490DS982F3 2753 11 0101 - Reserved - -54 11 0110 - Reserved - -55 11 0111 ZXNUMNum. Zero Crosses used for Line Freq. Y Y 0x00 006456 11 1000 - Res

CS549028 DS982F36.3 Software Registers Summary (Page 16)Address2RA[5:0] Name Description1DSP3HOST3Default0* 00 0000 Config2 Configuration 2 Y Y 0x 10

CS5490DS982F3 2953 11 0101 - Reserved -54* 11 0110 TGAINTemperature Gain Y Y 0x 06 B71655* 11 0111 TOFFTemperature Offset Y Y 0x D5 399856* 11 1000 -

CS5490DS982F3 35.9 Anti-creep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.10

CS549030 DS982F36.4 Software Registers Summary (Page 17)Address2RA[5:0] Name Description1DSP3HOST3Default0* 00 0000 VSagDURV Sag Duration Y Y 0x 00 0

CS5490DS982F3 316.5 Software Registers Summary (Page 18)Address2RA[5:0] Name Description1DSP3HOST3Default24* 01 1000 IZXLEVELI-channel Zero-crossing

CS549032 DS982F36.6 Register Descriptions21. “Default” = bit states after power-on or reset22. DO NOT write a “1” to any unpublished register bit or

CS5490DS982F3 336.6.2 Configuration 1 (Config1) – Page 0, Address 1 Default = 0x00 EEEE[23:21] Reserved.EPG_ON Enable EPG block.0 = Disable energy pu

CS549034 DS982F36.6.3 Configuration 2 (Config2) – Page 16, Address 0 Default = 0x10 0200[23] Reserved.POS Positive energy only. Suppress negative v

CS5490DS982F3 356.6.4 Phase Compensation (PC) – Page 0, Address 5 Default = 0x00 0000[23:22] Reserved.CPCC[1:0] Coarse phase compensation control for

CS549036 DS982F36.6.6 Pulse Output Width (PulseWidth) – Page 0, Address 8Default = 0x00 0001 (265.6µs at OWR = 4kHz)PulseWidth sets the energy pulse

CS5490DS982F3 376.6.8 Pulse Output Control (PulseCtrl) – Page 0, Address 9 Default = 0x00 0000This register controls the input to the energy pulse ge

CS549038 DS982F36.6.10 Phase Sequence Detection and Control (PSDC) – Page 0, Address 48 Default = 0x00 0000DONE Indicates valid count values reside i

CS5490DS982F3 396.6.12 Interrupt Status (Status0) – Page 0, Address 23Default = 0x 00 0000The Status0 register indicates a variety of conditions with

CS54904 DS982F3LIST OF FIGURESFigure 1. Oscillator Connections...

CS549040 DS982F36.6.13 Interrupt Mask (Mask) – Page 0, Address 3 Default = 0x00 0000The Mask register is used to control the activation of the INT p

CS5490DS982F3 416.6.15 Chip Status 2 (Status2) – Page 0, Address 25Default = 0x00 0000This register indicates a variety of conditions within the chip

CS549042 DS982F36.6.17 No Load Threshold (LoadMIN) – Page 16, Address 58 Default = 0x00 0000LoadMIN is used to set the no-load threshold for the anti

CS5490DS982F3 436.6.21 System Gain (SysGAIN) – Page 16, Address 60 Default = 0x50 0000 (1.25)System Gain (SysGAIN) is applied to all channels. By def

CS549044 DS982F36.6.25 Voltage Sag Level (VSagLEVEL) – Page 17, Address 1 Default = 0x00 0000Voltage sag level, VSagLEVEL, establishes an input level

CS5490DS982F3 456.6.29 Voltage Swell Level (VSwellLEVEL ) – Page 18, Address 47 Default = 0x7F FFFFVoltage swell level, VSwellLEVEL, establishes an i

CS549046 DS982F36.6.33 Active Power (PAVG) – Page 16, Address 5Default = 0x00 0000Instantaneous power is averaged over each low-rate interval (Sample

CS5490DS982F3 476.6.37 Instantaneous Quadrature Power (Q) – Page 16, Address 15Default = 0x00 0000Instantaneous quadrature power, Q, the product of V

CS549048 DS982F36.6.41 Power Factor (PF) – Page 16, Address 21 Default = 0x00 0000Power factor (PF) is calculated by dividing active power (PAVG) by

CS5490DS982F3 496.6.45 Total Reactive Power (QSUM) – Page 16, Address 31 Default = 0QSUM=QAVG This is a two's complement value in the range of -

CS5490DS982F3 51. OVERVIEWThe CS5490 is a CMOS power measurement integrated circuit that uses two  analog-to-digitalconverters to measure line volta

CS549050 DS982F36.6.49 Gain for Voltage (VGAIN) – Page 16, Address 35Default = 1.0Gain register VGAIN is initialized to 1.0 on reset. During gain cal

CS5490DS982F3 516.6.54 Temperature Offset (TOFF) – Page 16, Address 55Default = 0xD5 3998Register TOFF is used to offset the Temperature register (T)

CS549052 DS982F37. SYSTEM CALIBRATIONComponent tolerances, residual ADC offset, andsystem noise require a meter that needs to be calibratedbefore it m

CS5490DS982F3 53result in the AC offset register. This AC offset will besubtracted from RMS measurements in subsequentconversions, removing the AC off

CS549054 DS982F36) If the phase offset is negative, then the delay shouldbe added only to the current channel. Otherwise, addmore delay to the voltage

CS5490DS982F3 558. BASIC APPLICATION CIRCUITSThe CS5490 is configured to measure power in asingle-phase, two-wire single voltage and currentsystem, as

CS549056 DS982F39. PACKAGE DIMENSIONSNotes:1. Controlling dimensions are in millimeters.2. Dimensions and tolerances per ASME Y14.5M.3. This drawing

CS5490DS982F3 5710. ORDERING INFORMATION 11. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specified

CS54906 DS982F32. PIN DESCRIPTION 2.1 Analog PinsThe CS5490 has two differential inputs, one for voltage(VIN) and one for currentIIN). The CS

CS5490DS982F3 72.1.3 Voltage Reference The CS5490 generates a stable voltage reference of2.4V between the VREF pins. The reference systemalso requir

CS54908 DS982F33. CHARACTERISTICS & SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSPOWER MEASUREMENT CHARACTERISTICSNotes: 1. Specifications guaran

CS5490DS982F3 9-1-0.500.510 500 1000 1500 2000 2500 3000 3500 4000 4500Percent Error (%)Current Dynamic Range (x : 1)Lagging sin(੮) = 0.5Leading sin(੮