Cirrus-logic CS5508 Manuel d'utilisateur

1Copyright © Cirrus Logic, Inc. 1997(All Rights Reserved)Cirrus Logic, Inc.Crystal Semiconductor Products DivisionP.O. Box 17847, Austin, Texas 78760(

3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX VA+ = 5V ± 10%; VD+ = 3.3V ±5%; VA- = -5 V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL

XINXIN/2CONVSTATEtcd1tdd1MSB MSB-1pl1tph1tfd2tLSB+1 LSBConversion2STATE (CONV held high)SDATA(o)SCLK(o)Conversion1CSDRDYStandbyStandby Conversion Conv

RECOMMENDED OPERATING CONDITIONS (DGND = 0V) (Note 19)Parameter Symbol Min Typ Max UnitsDC Power Supplies: Positive Digital(VA+)-(VA-)Positive Analo

GENERAL DESCRIPTIONThe CS5505/6/7/8 are very low power mono-lithic CMOS A/D converters designedspecifically for measurement of dc signals. TheCS5505/7

slope to be used to properly scale the outputdigital codes when doing conversions. The calibration state is entered whenever theCAL and CONV pins are

AIN1. The BP/UP pin is not a latched input. TheBP/UP pin controls how the output word fromthe digital filter is processed. In bipolar modethe output w

External reference voltages can range from 1.0volt minimum to 3.6 volts maximum. The com-mon mode voltage range of the externalreference can allow the

Understanding Converter CalibrationCalibration can be performed at any time. Acalibration sequence will minimize offset errorsand set the gain slope s

Analog Input Impedance ConsiderationsThe analog input of the CS5505/6/7/8 can bemodeled as illustrated in Figure 8 (the model ig-nores the multiplexe

Digital Filter CharacteristicsThe digital filter in the CS5505/6/7/8 is the com-bination of a comb filter and a low pass filter.The comb filter has ze

ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =3.3V ± 5%; VREF+ = 2.5V(external); VREF- = 0V; fCLK = 32.768kHz; Bipo

If the CS5505/6/7/8 is operated at a clock rateother than 32.768 kHz, the filter characteristics,including the comb filter zeros, will scale withthe o

with other crystals in the range of 30 kHz to53 kHz. Over the military temperature range (-55 to +125 °C) the on-chip gate oscillator isdesigned to wo

Synchronous External-Clocking ModeThe serial port operates in the SEC mode whenthe M/SLP pin is connected to the DGND pin.SDATA is the output pin for

analog ground pin. No analog ground pin is re-quired because the inputs for measurement andfor the voltage reference are differential and re-quire no

Figure 14 illustrates the System Connection Dia-gram for the CS5505/6 using a single +5Vsupply. Note that all supply pins are bypassedwith 0.1 µF capa

CS5505/6+10VAnalogSupplyVD+VA+M/SLPSCLKSDATACALVREF+VREF-DGNDVA-DRDYCSA0A1BP/UPAIN1+AIN-AIN2+AIN3+AIN4+CONVNote:XINXOUT(1) To use the internal 2.5 vo

PIN CONNECTIONS*123452414131918171615678910121120212223CS5505/61234520151413121167891016171819CS5507/8MULTIPLEXER SELECTION INPUT A0 A1 MULTIPLEXER SE

PIN DESCRIPTIONSPin numbers for four channel devices are in parentheses.Clock GeneratorXIN; XOUT - Crystal In; Crystal Out, Pins 4 (5) and 5 (6).A gat

Control Input PinsCAL - Calibrate, Pin 3 (4).When taken high the same time that the CONV pin is taken high the converter will perform aself-calibratio

VD+ - Positive Digital Power, Pin 17 (20).Positive digital supply voltage. Nominally +5 volts or 3.3 volts.DGND - Digital Ground, Pin 16 (19).Digital

ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5 V ± 10%; VD+ =3.3V ± 5%; VREF+ = 2.5V (external); VREF- = 0V; fCLK = 32.768kHz ; B

CS5505/6/7/830 DS59F7ORDERING INFORMATION ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specified by I

CS5505/6/7/8DS59F7 31REVISION HISTORY Revision Date ChangesF4 MAR 1995 First Final ReleaseF5 AUG 2005 Updated device ordering info. Updated legal noti

CS5505/6/7/832 DS59F7- NOTES -

33Copyright © Cirrus Logic, Inc. 1998(All Rights Reserved)Cirrus Logic, Inc.Crystal Semiconductor Products DivisionP.O. Box 17847, Austin, Texas 78760

IntroductionThe CDB5505/6/7/8 evaluation board provides aquick means of testing the CS5505/6/7/8 seriesA/D converters. The CS5505/6/7/8 convertersrequ

Figure 1. ADC Connections0.01 µFC60.1 µF1A1B2A2B3AC80.1 µF6542LT1019-2.5 V+5C90.1 µFExternalVREF+_R825k3BVA+VA- DGNDVD+XIN XOUTM/SLPBP/UPSCLKSDATACALC

for A0 and A1 (see Table 1). Once A0 and A1are selected, the CONV switch (S2-3) must beswitched on (closed) and then open to cause theCONV signal to t

Figure 3. Top Ground Plane Layer (NOT TO SCALE)CS5505/6/7/8DS59DB2 37CDB5505/6/7/8DS59DB4 37CDB No Longer Available For Reference Only

Figure 4. Bottom Trace Layer (NOT TO SCALE)CS5505/6/7/838 DS59DB2CDB5505/6/7/838 DS59DB4CDB No Longer Available For Reference Only

Figure 5. Silk Screen Layer (NOT TO SCALE)CS5505/6/7/8DS59DB2 39CDB5505/6/7/8DS59DB4 39CDB No Longer Available For Reference Only

ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5 V ± 10%; VD+ =3.3V ± 5%; VREF+ = 2.5V (external); VREF- = 0V; fCLK = 32.768kHz ;

CDB5505/6/7/840 DS59DB4REVISION HISTORY Revision Date ChangesDB2 MAR 1995 First ReleaseF5 AUG 2005 Updated legal notice.DB4 JUN 2009 Removed referenc

5V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+VD+ = 5V ± 10%; VA-= -5V ± 10%;DGND = 0.) All measurements below are performed under static condi

5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (No

3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX VA+ = 5V ± 10%;VD+ = 3.3V ± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+ ; CL

tccwXINCalibration StandbyStandbytscltcalXIN/2STATECALCONVFigure 1. Calibration Timing (Not to Scale)tbuhXINXIN/2Conversion StandbyStandbyCONVSTATEts

5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Not