Cirrus-logic CS43122 Manuel d'utilisateur télécharger pdf (Page 11)

CS43122

SWITCHING CHARACTERISTICS - CONTROL PORT

= 25° C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, C

= 30 pF)

Notes: 9. t

spi

only needed before first falling edge of CS after RST rising edge. t

spi

= 0 at all other times.

10. Data must be held for sufficient time to bridge the transition time of CCLK.

11. For F

SCK

< 1 MHz

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency f

sclk

-6MHz

RST

Rising Edge to CS Falling t

srs

500 - ns

CCLK Edge to CS

Falling (Note 9) t

spi

500 - ns

High Time Between Transmissions t

csh

1.0 - µs

Falling to CCLK Edge t

css

20 - ns

CCLK Low Time t

scl

66 - ns

CCLK High Time t

sch

66 - ns

CDIN to CCLK Rising Setup Time t

dsu

40 - ns

CCLK Rising to DATA Hold Time (Note 10) t

15 - ns

Rise Time of CCLK and CDIN (Note 11) t

-100ns

Fall Time of CCLK and CDIN (Note 11) t

-100ns

CCLK Falling to CDOUT valid t

45 ns

dsu

sch

scl

CCLK

CDIN

css

csh

spi

srs

RST

Figure 3. SPI Control Port Timing

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 27 28

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Cirrus-logic CS43122 Manuel d'utilisateur Page 11

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