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Simplifying System Design Using the CS4350 PLL DAC

1. INTRODUCTION

Typical Digital to Analog Converters (DACs) require a high-speed Master Clock to clock their digital filters and mod-

ulators, as well as some portions of their discrete time analog circuitry. This Master Clock (or system clock) is typi-

cally required to be synchronous to the left-right (frame or word) clock (LRCK) in order to maintain sample alignment

in the digital filters, state machines, modulator and discrete time analog sections. Figure 1 below shows an example

of a typical DAC clocked by an external Master Clock. The clock is applied to the MCLK pin and then distributed to

any internal logic that requires it.

As an alternative, PLL DACs are designed to derive their internal synchronous Master Clock from some other ex-

ternal source. This source could be any clock, but in practice it is commonly a video clock (27 MHz) or one of the

slower SCLK or LRCK signals which are mandatory for typical PCM audio interfaces (See AN282 “The 2-Channel

Serial Audio Interface: A Tutorial”). In practice, the CS4350 PLL DAC generates its Master Clock from the input left-

right clock. Figure 2 shows the CS4350 PLL DAC architecture; from the input LRCK signal, the internal PLL derives

the Master Clock signal that is used to drive the internal system timing.

The internal Master Clock generation of a PLL DAC yields inherent benefits that simplify the design of audio sys-

tems. The CS4350’s unique implementation of the feature takes the concept a step further to provide an even great-

er degree of design simplicity, flexibility, and performance.

PCM

Serial

Interface

Serial Data Input

Right

Channel

Output

Left

Channel

Output

Left-Right Clock

Master Clock

Interpolation

Filter with

Volume

Control

Interpolation

Filter with

Volume

Control

Multibit ΔΣ

Modulator

Multibit ΔΣ

Modulator

Amp

Filter

Amp

Filter

DAC

Serial Clock

Figure 1. Typical DAC Architecture with Master Clock Input

PCM

Serial

Interface

Serial Data Input

Right

Channel

Output

Left

Channel

Output

Left-Right Clock

Recovered MCLK

Phase

Locked

Loop

Interpolation

Filter with

Volume

Control

Interpolation

Filter with

Volume

Control

Multibit ΔΣ

Modulator

Multibit ΔΣ

Modulator

Amp

Filter

Amp

Filter

DAC

Serial Clock

Internal MCLK

Figure 2. CS4350 PLL DAC Architecture

AN306

AUG '09

AN306REV1

1 2 3 4 5 6

Résumé du contenu

Page 1 - 1. INTRODUCTION

Page 2 - 3. LOCKING TO LRCK

2 AN306REV1AN3062. SIMPLIFIED SYSTEM DESIGNIn the design and layout of an audio mixed signal system, the conditioning and routing of the clocks are on

Page 3

AN306REV1 3AN3065. LOCALIZED MASTER CLOCK RECOVERY AND DISTRIBUTIONThe Recovered Master Clock (RMCK) output is a unique feature of the CS4350. The RMC

Page 4 - 8. CONCLUSIONS

4 AN306REV1AN3066. OUT-OF-BAND PERFORMANCEConverters that rely on an external Master Clock signal are often only able to operate with an internal over

Page 5 - REVISION HISTORY

AN306REV1 5AN306REVISION HISTORY Revision ChangesREV1 Initial Release

Page 6 - 6 AN306REV1

6 AN306REV1AN306Contacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one n

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Cirrus-logic AN306 Manuel d'utilisateur

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