Cirrus-logic CS43122 Manuel d'utilisateur

Advance Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without notice.

CS4312210SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25° C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, CL = 30 pF)Notes: 8. D

CS4312211SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25° C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, CL = 30 pF)Notes: 9. t

CS43122122. TYPICAL CONNECTION DIAGRAMSCLKAudioDataProcessorExternal ClockMCLKAGNDAOUTR+CS43122SDATAVAAOUTR-+5.5V0.1µF+ModeSelectM1M0AOUTL-AOUTL+DGNDV

CS43122133. REGISTER DESCRIPTION3.1 MODE CONTROL REGISTER (ADDRESS 01H)4.11 Differential DC offset calibration (CAL)Default = 00 - Disabled1 - Enabled

CS43122144.14 Power Down (PDN)Default = 10 - Disabled1 - EnabledFunction:The analog and digital sections will be placed into a power-down mode when th

CS43122154. PIN DESCRIPTIONRST1Reset (Input) - The device enters a low power mode and all internal state machines registers are reset when low. When h

CS4312216MCLK10Master Clock (Input) - The master clock frequency must be either 256x, 384x, 512x or 768x the input sample rate in Operational Mode 0;

CS4312217MUTE15Soft Mute (Input) - The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cycles in Opera

CS4312218AD1/CDIN(Control Port Mode)3Address Bit 1 / Control Data Input (Input) - In 2 Wire Mode, AD1 is a chip address bit. CDIN is the control data

CS43122195. APPLICATIONS5.1 Recommended Power-up Sequence1) Hold RST high until the power supplies, masterclock, and left/right clock are stable.2) Br

CS431222TABLE OF CONTENTS1. CHARACTERISTICS/SPECIFICATIONS ... 4ANALOG

CS43122206.3 Memory Address Pointer (MAP)INCR (Auto MAP Increment Enable) MAP0-2 (Memory Address Pointer)Default = ‘0’ Default = ‘001’0 - Disabled1 -

CS4312221M4 M1(DIF1)M0(DIF0)DESCRIPTION FORMAT FIGURE0 0 0 Left Justified, up to 24-bit data 0 2000 1I2S, up to 24-bit data1210 1 0 Right Justified, 1

CS4312222 -160-140-120-100-80-60-40-2000.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.6Frequency (nor

CS4312223-160-140-120-100-80-60-40-2000.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1Frequency (normalized to Fs)Amplitude dB-160-140-120-100-

CS4312224 LRCKSCLKLeft ChannelRight ChannelSDATA +3 +2 +1LSB+5 +4MSB-1 -2 -3 -4 -5+3 +2 +1LSB+5 +4MSB-1 -2 -3 -4Figur

CS43122257. PARAMETER DEFINITIONSTotal Harmonic Distortion + Noise (THD+N)The ratio of the rms value of the signal to the rms sum of all other spectr

CS43122269. PACKAGE DIMENSIONSINCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA 0.093 0.098 0.104 2.35 2.50 2.65A1 0.004 0.008 0.012 0.10 0.20 0.30b 0.0

• Notes •

CS431223LIST OF FIGURESFigure 1. Serial Audio Input Timing ...

CS4312241. CHARACTERISTICS/SPECIFICATIONSANALOG CHARACTERISTICS (TA = 25° C; Logic "1" = VD = 3 V; VA = 5.5 V;VREF=5.5 V Logic "0"

CS431225ANALOG CHARACTERISTICS (CONTINUED)Parameter Symbol Min Typ Max UnitDynamic Performance - Operational Mode 0 (Fs = 48 kHz) Dynamic Range (Note

CS431226 ANALOG CHARACTERISTICS (CONTINUED)Notes: 1. Triangular PDF dithered data.2. Performance limited by 16-bit quantization noise.3. Valid with t

CS431227ANALOG CHARACTERISTICS (Continued) Notes: 4. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 7-18)

CS431228DIGITAL CHARACTERISTICS (TA = 25° C; VD = 3.0 V - 5.25 V)ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.)WARNING:

CS431229SWITCHING CHARACTERISTICS (TA= -10 to 70° C; Logic 0 = AGND = DGND; Logic 1 = VD = 5.25 to 3.0 Volts; CL=20pF) Parameter Symbol Min Typ Max U