Cirrus-logic CS4244 Manuel d'utilisateur

Copyright  Cirrus Logic, Inc. 2012(All Rights Reserved)http://www.cirrus.com4 In/4 Out Audio CODEC with PCM and TDM InterfacesDAC Features Advanced

DS900F1 10CS4244TYPICAL CURRENT CONSUMPTIONThis table represents the power consumption for individual circuit blocks within the CS4244. CS4244 is conf

DS900F1 11CS4244ANALOG INPUT CHARACTERISTICS (COMMERCIAL GRADE)Test Conditions (unless otherwise specified): Device configured as shown in Section 2.

DS900F1 12CS4244ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE GRADE)Test Conditions (unless otherwise specified): Device configured as shown in Section 2.

DS900F1 13CS4244Figure 3. Test Circuit for ADC Performance TestingFigure 4. PSRR Test Configuration100 k4.7 uF100 k100 k470 pF634 90 .9 Analo

DS900F1 14CS4244ADC DIGITAL FILTER CHARACTERISTICSTest Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 7. In

DS900F1 15CS4244ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL GRADE)Test Conditions (unless otherwise specified). Device configured as shown in Section 2.

DS900F1 16CS4244ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE GRADE)Test Conditions (unless otherwise specified): Device configured as shown in Section 2.

DS900F1 17CS4244COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSETest Conditions (unless otherwise specified): VA_SEL = 0 for VA = 3.3 V

DS900F1 18CS4244DIGITAL I/O CHARACTERISTICSParameters Symbol Min Typ Max UnitsHigh-Level Input Voltage (all input pins except RST)(% of VL)(VL=1.8V)V

DS900F1 19CS4244SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACEVA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.Notes:25. After applying power to th

DS900F1 2CS4244TABLE OF CONTENTS1. PIN DESCRIPTIONS ...

DS900F1 20CS4244Figure 6. TDM Serial Audio Interface Timing SDOUT1(output )SDINx(input )tdsSCLK(input )FS/LRCK(input )MSBtdh1MSB-1tlckstdh2MSB MSB-1t

DS900F1 21CS4244SWITCHING SPECIFICATIONS - CONTROL PORTTest conditions (unless otherwise specified): Inputs: Logic 0 = GND = 0 V, Logic 1 = VL; SDA lo

DS900F1 22CS42444. APPLICATIONS4.1 Power Supply Decoupling, Grounding, and PCB LayoutAs with any high-resolution converter, the CS4244 requires carefu

DS900F1 23CS42444.2.2 Power-downTo prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turn-ing off the pow

DS900F1 24CS4244and 16, the VQ voltage will never rise to its minimum operating voltage. If the VQ voltage never risesabove this minimum operating vol

DS900F1 25CS4244The signal timings for a read and write cycle are shown in Figure 11 and Figure 12. A Start condition is de-fined as a falling transit

DS900F1 26CS42444.3.1 Memory Address Pointer (MAP)The MAP byte comes after the address byte and selects the register to be read or written. Refer to t

DS900F1 27CS42444.4.2 Master Mode Clock RatiosAs a clock master, FS/LRCK and SCLK will operate as outputs internally derived from MCLK. FS/LRCKis equa

DS900F1 28CS42444.5 Serial Port InterfaceThe serial port interface format is selected by the Serial Port Format register bits. The TDM format is avail

DS900F1 29CS4244 SDIN1Input Data 1.1 [31:8]x [7:0]Input Data 1.2 [31:8]x [7:0]Input Data 1.3 [31:8]x [7

DS900F1 3CS4244LIST OF FIGURESFigure 1. CS4244 Pinout ...

DS900F1 30CS42444.5.2 Left Justified and I²S ModesThe serial port of the CS4244 supports the Left Justified and I²S interface formats with valid bit d

DS900F1 31CS42444.6 Internal Signal Path The CS4244 device includes two paths in which audio data can be routed. The analog input path, shown inyellow

DS900F1 32CS4244 In Left Justified or I²S mode, the CS4244 transmits the AIN1 and AIN2 signals on the SDOUT1 pin andthe AIN3 and AIN4 signals on the S

DS900F1 33CS4244DAC1-4 Source [2:0] DAC1-4 Data is in:000 Slots 1-4 of SDIN1001 Slots 5-8 of SDIN1010Slots 9-12 of SDIN1011Slots 13-16 of SDIN1100Slot

DS900F1 34CS4244111 Slots 13-16 of SDIN2101Slots 5-8 of SDIN2110Slots 9-12 of SDIN2011Slots 13-16 of SDIN1100Slots 1-4 of SDIN2001 Slots 5-8 of SDIN10

DS900F1 35CS42444.6.2 ADC Path 4.6.2.1 Analog InputsAINx+ and AINx- are line-level differential analog inputs. The analog input pins do not self-bia

DS900F1 36CS42444.6.2.3 ADC HPFThe ADC path contains an optional HPF which can be enabled or disabled for all four ADCs via the “EN-ABLE HPF” bit in t

DS900F1 37CS42444.6.3 DAC1-4 Path The AOUT1-4 signals are driven by the data placed into the DAC1-4 path. This data can be placed intothe DAC1-4 pat

DS900F1 38CS4244De-emphasis is only available in Single-speed Mode. 4.6.4 Analog OutputsThe recommended differential passive output filter is shown

DS900F1 39CS42444.6.5 Volume ControlThe CS4244 includes a volume control for the DAC1-4 signal path. The implementation details for the vol-ume contro

DS900F1 4CS4244LIST OF TABLESTable 1. Speed Modes ...

DS900F1 40CS4244noise is avoided. In this mode the soft ramp algorithm linearly interpolates the volume between the volumechanges. There is a lag of o

DS900F1 41CS4244tracking and always produce a constant ramp rate. To accomplish this, set the MIN DELAY[2:0] and MAXDELAY[2:0] values to match the MUT

DS900F1 42CS4244When the upper “x” bits, as dictated by the DAC1-4 NG[2:0] settings, are either all “1’s” or all “0’s” for 8192consecutive samples, th

DS900F1 43CS42444.8.1 Interrupt MaskingAn occurrence of any of the errors mentioned above will cause the interrupt line to engage in order to no-tify

DS900F1 44CS4244USER: Mask bit(s) set to 0Unmasked error occursStatus Register bit changes to ‘1’ and INT pin set to active levelUSER: Read Status Re

DS900F1 45CS42445. REGISTER QUICK REFERENCEDefault values are shown below the bit names.AD Function 7 6 5 4 3 2 1 0 (Read Only Bits are shown in Ita

DS900F1 46CS424416h VolumeMode MUTE DELAY[1:0] MIN DELAY[2:0] MAX DELAY[2:0] p541 0 0 0 0 1 1 1 17h MasterVolume MASTER VOLUME[7:0] p550 0 0 1 0

DS900F1 47CS42446. REGISTER DESCRIPTIONSAll registers are read/write unless otherwise stated. All “Reserved” bits must maintain their default state. D

DS900F1 48CS42446.3 Clock & SP Select (Address 06h)6.3.1 Base Rate AdvisoryAdvises the CS4244 of the base rate of the incoming base rate. This all

DS900F1 49CS42446.4 Sample Width Select (Address 07h)6.4.1 Output Sample WidthThese bits set the width of the samples placed into the outgoing SDOUTx

DS900F1 5CS42441. PIN DESCRIPTIONS Figure 1. CS4244 PinoutPin Name Pin # Pin DescriptionSDA 1 Serial Control Data (Input/Output) - Bi-directional da

DS900F1 50CS42446.5.3 Serial Data Output SidechainSetting this bit enables the SDOUT1 side chain feature. In this mode, the samples from multiple devi

DS900F1 51CS42446.7 ADC Control 1 (Address 0Fh)6.7.1 VA SelectScales internal operational voltages appropriately for VA level. Configuring this bit ap

DS900F1 52CS42446.9 DAC Control 1 (Address 12h)6.9.1 DAC1-4 Noise GateThis sets the bit depth at which the Noise Gate feature should engage for the DA

DS900F1 53CS42446.11 DAC Control 3 (Address 14h)6.11.1 DAC1-4 AttenuationSets the mode of attenuation used for the DAC1-4 path.Note: Please see Sectio

DS900F1 54CS42446.13 Volume Mode (Address 16h)6.13.1 Mute DelaySets the delay between the volume steps during muting and unmuting of a signal when att

DS900F1 55CS42446.14 Master and DAC1-4 Volume Control (Address 17h, 18h, 19h, 1Ah, & 1Bh)6.14.1 x Volume ControlSets the level of the x Volume Con

DS900F1 56CS42446.16 Interrupt Mask 1 (Address 1Fh)6.16.1 Test Mode Error Interrupt MaskControls whether a Test Mode Error event flags the interrupt p

DS900F1 57CS42446.17 Interrupt Mask 2 (Address 20h)6.17.1 DACx Clip Interrupt MaskAllows or prevents a DACx Clip event from flagging the interrupt pin

DS900F1 58CS42446.19 Interrupt Notification 2 (Address 22h) (Read Only)6.19.1 DACx Clip A DACx Clip has occurred since the last clearing of the Interr

DS900F1 59CS42447. ADC FILTER PLOTS0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1−100−90−80−70−60−50−40−30−20−100Frequency (normalized to Fs)Amplitude (dB)St

DS900F1 6CS42441.1 I/O Pin CharacteristicsInput and output levels and associated power supply voltage are shown in the table below. Logic levelsshould

DS900F1 60CS42448. DAC FILTER PLOTSFigure 38. SSM DAC Stopband Rejection Figure 39. SSM DAC Transition BandFigure 40. SSM DAC Transition Band (Deta

DS900F1 61CS4244Figure 42. DSM DAC Stopband Rejection Figure 43. DSM DAC Transition BandFigure 44. DSM DAC Transition Band (Detail)Figure 45. DSM

DS900F1 62CS42449. PACKAGE DIMENSIONS Figure 46. Package DrawingNotes: 1. Dimensioning and tolerance per ASME Y4.5M - 1994.2. Dimensioning lead width

DS900F1 63CS424410.ORDERING INFORMATION11.REVISION HISTORYProduct Description PackagePb-Free GradeTemp Range ContainerOrder#CS4244 4 In/4 Out CODEC 40

DS900F1 7CS42442. TYPICAL CONNECTION DIAGRAM Figure 2. Typical Connection DiagramCS4244AIN4-AIN3+AIN2-AIN3-VAFILT+AIN1+AIN1-AIN2+AIN4+SDOUT1VLGNDFS/

DS900F1 8CS42443. CHARACTERISTICS AND SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSGND = 0 V; all voltages with respect to ground. (Note 3)Notes: 3.

DS900F1 9CS4244DC ELECTRICAL CHARACTERISTICS GND = 0 V; all voltages with respect to ground. Notes:7. No external loads should be connected to the VD