Cirrus-logic CS42526 Manuel d'utilisateur

Copyright  Cirrus Logic, Inc. 2014 (All Rights Reserved)http://www.cirrus.com114 dB, 192-kHz 6-Ch CODEC with S/PDIF ReceiverFeatures Six 24-bit D/A,

10 DS585F2CS42526D/A DIGITAL FILTER CHARACTERISTICS Notes:9. Response is clock dependent and will scale with Fs. Note that the response plots (Fig

DS585F2 11CS42526SWITCHING CHARACTERISTICS(TA = -10 to +70° C; VA=VARX = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1

12 DS585F2CS42526SWITCHING CHARACTERISTICS - CONTROL PORT - I²C™ FORMAT(TA = -10 to +70° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inpu

DS585F2 13CS42526SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT (TA = -10 to +70° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inp

14 DS585F2CS42526DC ELECTRICAL CHARACTERISTICS(TA = 25° C; AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode)Notes:23. Cu

DS585F2 15CS42526DIGITAL INTERFACE CHARACTERISTICS(TA = +25° C)Notes:27. Serial Port signals include: RMCK, OMCK, SAI_SCLK, SAI_LRCK, SAI_SDOUT, CX_SC

16 DS585F2CS425262. PIN DESCRIPTIONS Pin Name # Pin DescriptionCX_SDIN1CX_SDIN2CX_SDIN316463Codec Serial Audio Data Input (Input) - I

DS585F2 17CS42526INT11Interrupt (Output) - The CS42526 will generate an interrupt condition as per the Interrupt Mask register. See “Interrupts” on pa

18 DS585F2CS42526ADCIN1ADCIN25857External ADC Serial Input (Input) - The CS42526 provides for up to two external stereo analog to digital converter in

DS585F2 19CS425263. TYPICAL CONNECTION DIAGRAM VDAOUTA1+240.1 µF+10 µF100 µF0.1 µF++1718VQFILT+36370.1 µF4.7 µFVA+10 µF51AOUTA1-AOUTB1+3534AOUTB

2 DS585F2CS42526TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ...

20 DS585F2CS425264. APPLICATIONS4.1 OverviewThe CS42526 is a highly integrated mixed-signal 24-bit audio codec comprised of 2 analog-to-digital con-ve

DS585F2 21CS425264.2.2 High-Pass Filter and DC Offset CalibrationThe high-pass filter continuously subtracts a measure of the DC offset from the outpu

22 DS585F2CS425264.3.3 Digital Volume and Mute ControlEach DAC’s output level is controlled via the Volume Control registers operating over the range

DS585F2 23CS425264.4 S/PDIF ReceiverThe CS42526 includes an S/PDIF digital audio receiver. The S/PDIF receiver accepts and decodes digitalaudio data a

24 DS585F2CS425264.5 Clock GenerationThe clock generation for the CS42526 is shown in the figure below. The internal MCLK is derived from theoutput of

DS585F2 25CS425264.5.2 OMCK System Clock ModeA special clock-switching mode is available that allows the clock that is input through the OMCK pin to b

26 DS585F2CS42526When either serial port is in Slave Mode, its respective LRCK signal must be present for proper deviceoperation.In Slave Mode, One-Li

DS585F2 27CS42526 Serial Inputs / OutputsCX_SDIN1 left channel right channel

28 DS585F2CS425264.6.2 Serial Audio Interface FormatsThe CODEC_SP and SAI_SP digital audio serial ports support five formats with varying bit depths f

DS585F2 29CS42526CX_LRCKSAI_LRCKCX_SCLKSAI_SCLKLeft ChannelRight ChannelCX_SDINxCX_SDOUTSAI_SDOUT+3 +2 +1+5 +4-1 -2 -3 -4 -5+3 +2 +1+5 +4-1-2 -3 -4MSB

DS585F2 3CS425266. REGISTER DESCRIPTION ...

30 DS585F2CS42526CX_LRCKSAI_LRCKCX_SCLKSAI_SCLKLSBMSB20 clks64 clks 64 clksLSBMSB LSBMSB LSBMSB LSBMSB LSBMSB MSBDAC1 DAC3 DAC5 DAC2 DAC4 DAC620 clks2

DS585F2 31CS425264.6.3 ADCIN1/ADCIN2 Serial Data FormatThe two serial data lines which interface to the optional external ADCs, ADCIN1 and ADCIN2, sup

32 DS585F2CS425264.6.4 One-Line Mode (OLM) Configurations4.6.4.1 OLM Config #1One-Line Mode Configuration #1 can support up to 6 channels of DAC data,

DS585F2 33CS425264.6.4.2 OLM Config #2This configuration will support up to 6 channels of DAC data or 6 channels of ADC data and no channelsof S/PDIF

34 DS585F2CS425264.6.4.3 OLM Config #3This One Line Mode configuration #3 will support up to 6 channels of DAC data, 6 channels of ADC data and 2 chan

DS585F2 35CS425264.6.4.4 OLM Config #4This configuration will support up to 6 channels of DAC data 6 channels of ADC data and no channels ofS/PDIF rec

36 DS585F2CS425264.6.4.5 OLM Config #5This One-Line Mode configuration can support up to 6 channels of DAC data 2 channels of ADC data and2 channels o

DS585F2 37CS425264.7 Control Port Description and TimingThe control port is used to access the registers, allowing the CS42526 to be configured for th

38 DS585F2CS425264.7.2 I²C ModeIn I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.There is no C

DS585F2 39CS42526Send start condition. Send 10011xx1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected r

4 DS585F2CS4252611. APPENDIX D: EXTERNAL AES3-S/PDIF-IEC60958 RECEIVER COMPONENTS ... 8211.1 AES3 Receiver External Components

40 DS585F2CS42526For applications where the output of the PLL is required to be low jitter, use a separate, low-noise analog+5 V supply for VARX, deco

DS585F2 41CS425265. REGISTER QUICK REFERENCEAddr Function 7 6 5 4 3 2 1 001hIDChip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0page

42 DS585F2CS425260FhVol. Control A1A1_VOL7 A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0page 58default0 0 00000 010hVol. Control B1B1_VOL7 B

DS585F2 43CS425261FhRCVR Mode Ctrl 2Reserved TMUX2 TMUX1 TMUX0 Reserved RMUX2 RMUX1 RMUX0page 63default0 0 00000 020hInterrupt StatusUNLOCK Reserved Q

44 DS585F2CS425262EhRXP2/GPO2Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0page 69default0 0 00000 02FhRXP1/GPO1Mode1 Mode0 Po

DS585F2 45CS425266. REGISTER DESCRIPTIONAll registers are read/write except for the I.D. and Revision Register, OMCK/PLL_CLK Ratio Register, Interrupt

46 DS585F2CS425266.3 Power Control (address 02h)6.3.1 POWER DOWN RECEIVER (PDN_RCVRX)Default = 1000 - Receiver and PLL in normal operational mode.01 -

DS585F2 47CS425266.4 Functional Mode (address 03h)6.4.1 CODEC FUNCTIONAL MODE (CODEC_FMX)Default = 0000 - Single-Speed Mode (4 to 50 kHz sample rates)

48 DS585F2CS42526Receiver Mode Control (address 1Eh) register to set the appropriate sample rate. 6.4.5 RECEIVER DE-EMPHASIS CONTROL (RCVR_DEM)Defaul

DS585F2 49CS425266.5 Interface Formats (address 04h)6.5.1 DIGITAL INTERFACE FORMAT (DIFX)Default = 01Function:These bits select the digital interface

DS585F2 5CS42526Figure 43. Quad-Speed Mode Transition Band ... 8

50 DS585F2CS425266.5.4 SAI RIGHT-JUSTIFIED BITS (SAI_RJ16)Default = 0Function:This bit determines how many bits to use during right-justified mode for

DS585F2 51CS425266.6.4 INTERPOLATION FILTER SELECT (FILT_SEL)Default = 0Function:This feature allows the user to select whether the DAC interpolation

52 DS585F2CS425266.7 Clock Control (address 06h)6.7.1 RMCK DIVIDE (RMCK_DIVX)Default = 00Function:Divides/multiplies the internal MCLK, either from th

DS585F2 53CS425266.7.4 MASTER CLOCK SOURCE SELECT (SW_CTRLX)Default = 00Function:These two bits, along with the UNLOCK bit in register “Interrupt Stat

54 DS585F2CS425266.9 RVCR Status (address 08h) (Read Only)6.9.1 DIGITAL SILENCE DETECTION (DIGITAL SILENCE)Default = x0 - Digital Silence not detected

DS585F2 55CS425266.9.4 RECEIVER CLOCK FREQUENCY (RCVR_CLKX)Default = xxxFunction:The CS42526 detects the ratio between the OMCK and the recovered cloc

56 DS585F2CS425266.11 Volume Transition Control (address 0Dh)6.11.1 SINGLE VOLUME CONTROL (SNGVOL)Default = 0Function:The individual channel volume le

DS585F2 57CS425266.11.3 AUTO-MUTE (AMUTE)Default = 10 - Disabled1 - EnabledFunction:The digital-to-analog converters of the CS42526 will mute the out

58 DS585F2CS425266.12 Channel Mute (address 0Eh)6.12.1 INDEPENDENT CHANNEL MUTE (XX_MUTE)Default = 00 - Disabled1 - EnabledFunction:The digital-to-ana

DS585F2 59CS42526Mixing Control Pair 2 (Channels A2 & B2) (address 19h)Mixing Control Pair 3 (Channels A3 & B3) (address 1Ah) 6.15.1 CHANNEL A

6 DS585F2CS425261. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Cond

60 DS585F2CS425266.15.2 ATAPI CHANNEL-MIXING AND MUTING (PX_ATAPIX) Default = 01001Function:The CS42526 implements the channel-mixing functions of the

DS585F2 61CS425266.16 ADC Left Channel Gain (address 1Ch)6.16.1 ADC LEFT CHANNEL GAIN (LGAINX)Default = 00hFunction:The level of the left analog chann

62 DS585F2CS425266.18.2 DE-EMPHASIS SELECT BITS (DE-EMPHX)Default = 0000 - Reserved01 - De-Emphasis for 32 kHz sample rate.10 - De-Emphasis for 44.1 k

DS585F2 63CS425266.19 Receiver Mode Control 2 (address 1Fh)6.19.1 TXP MULTIPLEXER (TMUXX)Default = 000Function:Selects which of the eight receiver inp

64 DS585F2CS425266.20.1 PLL UNLOCK (UNLOCK)Default = 0Function:PLL unlock status bit. This bit will go high if the PLL becomes unlocked.6.20.2 NEW Q-S

DS585F2 65CS425266.22 Interrupt Mode MSB (address 22h)Interrupt Mode LSB (address 23h)Default = 00000000Function:The two Interrupt Mode registers form

66 DS585F2CS425266.23.3 C-DATA BUFFER CONTROL (CAM)Default = 00 - One byte mode1 - Two byte modeFunction:Sets the C-data buffer control port access mo

DS585F2 67CS425266.24.2 CHANNEL STATUS BLOCK FORMAT (PRO)Default = xFunction:Indicates the channel status block format.6.24.3 AUDIO INDICATOR (AUDIO)D

68 DS585F2CS425266.25.3 PLL LOCK STATUS (UNLOCK)Default = x0 - PLL locked1 - PLL out of lockFunction:Indicates the lock status of the PLL.6.25.4 RECEI

DS585F2 69CS42526the status of the HOLD bit. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not appear in the receiv

DS585F2 7CS42526ANALOG INPUT CHARACTERISTICS(TA = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5 V; Mea-sur

70 DS585F2CS42526or as a dedicated ADC overflow pin indicating an over-range condition anywhere in the ADC signal path for either the left or right ch

DS585F2 71CS42526following table. It is recommended that in this mode the remaining functional bits be set to 0.GPO, Drive High - If the pin is config

72 DS585F2CS425267. PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over th

DS585F2 73CS425268. APPENDIX A: EXTERNAL FILTERS8.1 ADC Input FilterThe analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). Th

74 DS585F2CS425269. APPENDIX B: S/PDIF RECEIVER9.1 Error Reporting and Hold FunctionThe UNLOCK bit indicates whether the PLL is locked to the incoming

DS585F2 75CS425269.2.1 Channel Status Data E Buffer AccessThe user can monitor the incoming Channel Status data by reading the E buffer, which is mapp

76 DS585F2CS425269.2.2 Serial Copy Management System (SCMS)The CS42526 allows read access to all the channel status bits. For consumer mode SCMS compl

DS585F2 77CS4252610.APPENDIX C: PLL FILTERThe PLL has been designed to only use the preambles of the S/PDIF stream to provide lock update information

78 DS585F2CS42526The external PLL component values listed in Table 21 have a high corner-frequency jitter-attenuationcurve, take a short time to lock,

DS585F2 79CS4252610.1.2 Jitter AttenuationFigures 28 and 29 show the jitter-attenuation characteristics for the 32-192 kHz sample rate range whenused

8 DS585F2CS42526A/D DIGITAL FILTER CHARACTERISTICS Notes:5. The filter frequency response scales precisely with Fs.6. Response shown is for Fs equal

80 DS585F2CS4252610.1.3 Capacitor SelectionThe type of capacitors used for the PLL filter can have a significant effect on receiver performance. Large

DS585F2 81CS4252610.1.4 Circuit Board LayoutBoard layout and capacitor choice affect each other and determine the performance of the PLL. Figure30 ill

82 DS585F2CS4252611.APPENDIX D: EXTERNAL AES3-S/PDIF-IEC60958 RECEIVER COMPONENTS 11.1 AES3 Receiver External ComponentsThe CS42526 AES3 receiver is d

DS585F2 83CS4252612.APPENDIX E: ADC FILTER PLOTS -140-130-120-110-100-90-80-70-60-50-40-30-20-1000.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Frequency

84 DS585F2CS42526 -10-9-8-7-6-5-4-3-2-100.40 0.43 0.45 0.48 0.50 0.53 0.55Frequency (normalized to Fs)Amplitude (dB) -0.10-0.08-0.05-0.030.

DS585F2 85CS4252613.APPENDIX F: DAC FILTER PLOTS0.4 0.5 0.6 0.7 0.8 0.9 1120100806040200Frequency(normalized to Fs)Amplitude (dB)0.4 0.42 0.44 0.46 0.

86 DS585F2CS425260 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50.020.0150.010.00500.0050.010.0150.02Frequency(normalized to Fs)Amplitude (dB)0.45 0.46

DS585F2 87CS425260.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1120100806040200Frequency(normalized to Fs)Amplitude (dB)0.2 0.3 0.4 0.5 0.6 0.7 0.8120100806040200Fr

88 DS585F2CS425260.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55109876543210Frequency(normalized to Fs)Amplitude (dB)0 0.05 0.1 0.15 0.2 0.250.2

DS585F2 89CS4252614.PACKAGE DIMENSIONS THERMAL CHARACTERISTICSINCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA --- 0.55 0.063 --- 1.40 1.60A1 0.002 0.

DS585F2 9CS42526ANALOG OUTPUT CHARACTERISTICS(TA = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5V; Measure

90 DS585F2CS4252615.ORDERING INFORMATION16.REFERENCES1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997.http://www.cirrus.com

DS585F2 91CS4252617.REVISION HISTORY Release Date ChangesF1 October 2005Final Release– Added ordering information table on page 90.– Updated registers