Cirrus-logic CS4270 Manuel d'utilisateur

Copyright  Cirrus Logic, Inc. 2010 (All Rights Reserved)http://www.cirrus.com24-Bit, 192-kHz Stereo Audio CODECD/A Features High Performance– 105 dB

10 DS686F1CS4270DAC COMBINED INTERPOLATION & ANALOG FILTER RESPONSEThe filter characteristics have been normalized to the sample rate (Fs) and can

DS686F1 11CS4270ADC ANALOG CHARACTERISTICSTest Conditions (unless otherwise specified): VD = VL = 3.3 V, DGND = AGND = 0 V; TA = 25° C; 997 Hz Input S

12 DS686F1CS4270ADC DIGITAL FILTER CHARACTERISTICSMeasurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. (Note 9)Notes: 9. Plots of this

DS686F1 13CS4270DC ELECTRICAL CHARACTERISTICSTA = 25° C; AGND = DGND = 0 V, all voltages with respect to 0 V; MCLK = 12.288 MHz; Master Mode).Notes: 1

14 DS686F1CS4270SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACELogic "0" = DGND = AGND = 0 V; Logic "1" = VD, CL = 20 pF. Notes

DS686F1 15CS4270Figure 4. Master Mode, Left-Justified SAI Figure 5. Slave Mode, Left-Justified SAISCLK outputSDOUTLRCK outputMSB MSB-1 MSB-2 MSB-3tm

16 DS686F1CS4270Figure 9. Format 0, Left-Justified up to 24-Bit DataLRCKSCLKChannel A - Left SDATA+3 +2 +1LSB+5 +4MSB-1 -2 -3 -4 -5 +3 +2 +1LSB+5 +4M

DS686F1 17CS4270SWITCHING CHARACTERISTICS - SOFTWARE MODE - I²C FORMATInputs: Logic ‘0’ = AGND = DGND = 0 V, Logic ‘1’ = VLC, CL=30pFNote: 17. Data mu

18 DS686F1CS4270SWITCHING CHARACTERISTICS - SOFTWARE MODE - SPI FORMAT Inputs: Logic ‘0’ = AGND = DGND = 0 V; Logic ‘1’ = VLC; CL=20pF. Notes: 18. tsp

DS686F1 19CS42705. APPLICATIONS5.1 Stand-Alone Mode5.1.1 Access to Stand-Alone Mode Reliable power-up is achieved by keeping the device in reset until

2 DS686F1CS4270Stand-Alone Mode Feature Set System Features– Master or Slave Serial Audio Interface – Single-, Double-, or Quad-Speed OperationD/A F

20 DS686F1CS42705.1.4 Clock Ratio SelectionDepending on whether the CS4270 is in Master or Slave Mode, different MCLK/LRCK and SCLK/LRCKratios may be

DS686F1 21CS4270could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multi-channel system. I

22 DS686F1CS4270Clock-ratio configuration for each mode is outlined in the Table 11 on page 34 and Table 10 on page 33.In Serial Control Port Mode, th

DS686F1 23CS42705.2.5 Internal Digital LoopbackIn Serial Control Port Mode, the CS4270 supports an internal digital loopback mode in which the outputo

24 DS686F1CS42705.2.8 Oversampling ModesThe CS4270 operates in one of three oversampling modes based on the input sample rate. Mode selec-tion is dete

DS686F1 25CS42705.5 Analog ConnectionsThe analog modulator samples the input at 6.144 MHz for Fs = 48, 96, and 128 kHz and scales propor-tionally for

26 DS686F1CS4270220 pFAnalogInput10µFAINxCS4270+2 k(R1)2 k(R2)Figure 15. CS4270 Example Analog Input Network1 10-110-105-100-95-90-85-80-75-70-65-

DS686F1 27CS42705.5.2 Output ConnectionsThe analog output filter present in the CS4270 is a switched-capacitor low pass filter. Its response, com-bine

28 DS686F1CS42705.7 Synchronization of Multiple DevicesIn systems where multiple ADCs are required, care must be taken to achieve simultaneous samplin

DS686F1 29CS4270Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shownin Figure 21, the write operat

DS686F1 3CS4270TABLE OF CONTENTS1. PIN DESCRIPTIONS ...

30 DS686F1CS42701. Bring CS low.2. The address byte on the CDIN pin must then be 10011110 (R/W=0).3. Write to the memory address pointer, MAP. This by

DS686F1 31CS42706.2.3 Memory Address Pointer (MAP) The MAP byte comes after the address byte and selects the register to be read or written. Refer toF

32 DS686F1CS42708. REGISTER DESCRIPTION** All registers are read/write in I²C Mode and SPI Mode, unless otherwise noted**8.1 Device ID - Address 01hFu

DS686F1 33CS42708.3 Mode Control - Address 03h8.3.1 ADC Functional Mode & Master/Slave Mode (Bits 5:4)Function:In Master Mode, the user must confi

34 DS686F1CS42708.4 ADC and DAC Control - Address 04h8.4.1 ADC High Pass Filter Freeze for CH A (Bit 7)Function:When this bit is set, the internal hig

DS686F1 35CS42708.5 Transition Control - Address 05h8.5.1 DAC Single Volume (Bit 7)Function:The AOUTA and AOUTB volume levels are independently contro

36 DS686F1CS42708.5.4 De-Emphasis Control (Bit 0)Function:When this bit is set, the standard 50/15 s digital de-emphasis filter is applied on the DAC

DS686F1 37CS42708.8 DAC Channel B Volume Control - Address 08hFunction:The digital volume control allows the user to attenuate the signal in 0.5 dB in

38 DS686F1CS42709. FILTER PLOTS Figure 23. DAC Single-Speed Stopband Rejection Figure 24. DAC Single-Speed Transition Band0.45 0.46 0.47 0.48 0.

DS686F1 39CS4270 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55-10-9-8-7-6-5-4-3-2-101Frequency (normalized to Fs)Amplitude dB0 0.05 0.1 0.

4 DS686F1CS42701. PIN DESCRIPTIONS 1.1 Software ModePin Name # Pin DescriptionSDIN 1 Serial Audio Data Input (Input) - Input for two’s complement seri

40 DS686F1CS4270 Figure 35. ADC Single-Speed Stopband Rejection Figure 36. ADC Single-Speed Stopband (detail)-140-130-120- 110-100-90-80-70-60-5

DS686F1 41CS4270 Figure 41. ADC Double-Speed Transition Band (detail) Figure 42. ADC Double-Speed Passband Ripple-10-9-8-7-6-5-4-3-2-100.46 0.4

42 DS686F1CS427010.PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over the

DS686F1 43CS427011.PACKAGE DIMENSIONS1. “D” and “E1” are reference datums and do not include mold flash or protrusions, but do include moldmismatch an

44 DS686F1CS427012.ORDERING INFORMATION13.REVISION HISTORYProduct Description Package Pb-Free Temp Range Container Order #CS4270 24-Bit 192 kHz Stereo

DS686F1 45CS4270Contacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one n

DS686F1 5CS42701.2 Stand-Alone ModePin Name # Pin DescriptionSDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.LRC

6 DS686F1CS42702. DIGITAL I/O PIN CHARACTERISTICSThe level for each input is set by its corresponding power supply and should not exceed the maximum r

DS686F1 7CS42703. TYPICAL CONNECTION DIAGRAMFigure 1. CS4270 Typical Connection Diagram CS (I2S/LJ) /AD0SDA/CDOUT (M1)SCL/CCLK (M0)AINAAINBRSTPower D

8 DS686F1CS42704. CHARACTERISTICS AND SPECIFICATIONSSPECIFIED OPERATING CONDITIONSAGND = DGND= 0 V; all voltages with respect to ground.ABSOLUTE MAXIM

DS686F1 9CS4270DAC ANALOG CHARACTERISTICSTest Conditions (unless otherwise specified): VD = VL = 3.3 V, AGND = DGND = 0 V; TA = +25° C; Full-Scale Out