Cirrus-logic CDB4353 Manuel d'utilisateur

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Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
http://www.cirrus.com
Evaluation Board for the CS4353
Features
Demonstrates Recommended Layout and
Grounding Arrangements
CS8416 Receives S/PDIF, & EIAJ-340-
Compatible Digital Audio
Headers for External PCM Audio
Single-ended Stereo Analog Outputs
Requires Only a Digital Signal Source and a
+3.3 V Power Supply for a Complete Digital-to-
Analog Converter System
Configured by On-board Hardware Controls
Power, Digital Source Select, and S/PDIF Error
Indicator LEDs
Current Sense Resistors for CS4353 Supplies
(VA, VL, and VCP)
Description
The CDB4353 evaluation board is an excellent means
for quickly evaluating the CS4353 24-bit, high-perfor-
mance stereo D/A converter. Evaluation requires an
analog signal analyzer, a digital signal source, and a
+3.3 V power supply. Analog line-level outputs are pro-
vided via RCA phono jacks.
The CS8416 digital audio receiver IC provides the sys-
tem timing necessary to operate the Digital-to-Analog
converter and will accept S/PDIF and EIAJ-340-com-
patible audio data. The evaluation board may also be
configured to accept external timing and data signals for
operation in a user application during system
development.
The CDB4353 is controlled by switches to select the
digital signal source and configuration options for the
CS4353. Current sense resistors allow for easy power
calculations during system development.
ORDERING INFORMATION
CDB4353 Evaluation Board
Indicator LEDs
S/PDIF Error
S/PDIF or PCM Input Selected
+3.3V power
VL power
CS4353
CS8416
S/PDIF
Receiver
PCM Mux
and Level
Shifter
PCM Clocks/Data
PCM Clocks/Data
CS4353 Settings
PCM source select
CS8416 serial port
format
Analog Outputs
Hardware Control
Switches
Reset Circuit
CS4353 Reset
CS8416 Reset
External
System
Connector
PCM Clocks/DataPCM Clocks/Data
PCM Input
Optical
S/PDIF
Input
AOUTA
AOUTB
PCM Header
Coaxial
S/PDIF
Input
+3.3V Power
(Optional separate VL)
AUG '08
DS803DB2
CDB4353
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Résumé du contenu

Page 1 - Description

Copyright © Cirrus Logic, Inc. 2008(All Rights Reserved)http://www.cirrus.comEvaluation Board for the CS4353Features Demonstrates Recommended Layout

Page 2 - LIST OF FIGURES

10 DS803DB2CDB4353-150+0-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBr A20 20k50 100 200 500 1k 2k 5k 10kHz-33-2.5-2-1.5-1-500m0500m11.522.5V0 1.5

Page 3 - LIST OF TABLES

DS803DB2 11CDB4353-110+0-100-90-80-70-60-50-40-30-20-10dBr A20 20k50 100 200 500 1k 2k 5k 10kHz-110+0-100-90-80-70-60-50-40-30-20-10dBr A-120 +0-100 -

Page 4 - 4. INPUT FOR CLOCKS AND DATA

12 DS803DB2CDB435312.SCHEMATICS AND LAYOUT Indicator LEDs S/PDIF Error S/PDIF or PCM Input Selected +3.3V power VL powerCS4353CS8416S

Page 5

DS803DB2 13CDB4353Figure 32. CS8416 and CS4353

Page 6

14 DS803DB2CDB4353Figure 33. HW Configuration, PCM Header, and Power

Page 7 - 11.PERFORMANCE PLOTS

DS803DB2 15CDB4353Figure 34. Silkscreen Top

Page 8 - 8 DS803DB2

16 DS803DB2CDB4353Figure 35. Top Side

Page 9 - DS803DB2 9

DS803DB2 17CDB4353Figure 36. Bottom Side

Page 10 - 10 DS803DB2

18 DS803DB2CDB435313.REVISION HISTORY Release ChangesDB1 Initial ReleaseDB2 Updated block diagram on page 1 and Figure 31.Updated features and descrip

Page 11 - DS803DB2 11

2 DS803DB2CDB4353TABLE OF CONTENTS1. CDB4353 SYSTEM OVERVIEW ...

Page 12 - 12 DS803DB2

DS803DB2 3CDB4353LIST OF TABLESTable 1. Switch S1 Quick Setup ...

Page 13 - DS803DB2 13

4 DS803DB2CDB43531. CDB4353 SYSTEM OVERVIEWThe CDB4353 evaluation board is an excellent means of quickly evaluating the CS4353. The CS8416 digital aud

Page 14 - 14 DS803DB2

DS803DB2 5CDB43535. POWER SUPPLY CIRCUITRYPower is supplied to the evaluation board by two binding posts, GND and +3.3 V (see Figure 33). The allowabl

Page 15 - DS803DB2 15

6 DS803DB2CDB435310.BOARD CONNECTIONS AND SETTINGSBoard connections and settings are shown in Table 2, Table 3, and Table 4 below. Table 2. System Co

Page 16 - 16 DS803DB2

DS803DB2 7CDB435311.PERFORMANCE PLOTSTest conditions (unless otherwise specified): TA = 25°C; VCP = VA = VL = 3.3 V; AGND = DGND =CPGND = 0 V;OPT1 S/P

Page 17 - DS803DB2 17

8 DS803DB2CDB4353-40+40-35-30-25-20-15-10-5+0+5+10+15+20+25+30+35dBr A-140 +0-120 -100 -80 -60 -40 -20dBFS-5+5-4-3-2-1+0+1+2+3+4dBr A20 20k50 100 200

Page 18 - 13.REVISION HISTORY

DS803DB2 9CDB4353-150+0-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBr A20 20k50 100 200 500 1k 2k 5k 10kHz-150+0-140-130-120-110-100-90-80-70-60-5

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