Cirrus-logic AN269 Manuel d'utilisateur

Copyright © Cirrus Logic, Inc. 2005(All Rights Reserved)http://www.cirrus.comUsing the EP93xx's Raster Engine1. INTRODUCTION AND SCOPEThe purpose

10 AN269REV1AN269The output mode “Single 16-bit 565 Pixel Per Clock” is shown in Figure 3. In this mode, each SPCLK will clock outa single pixel, with

AN269AN269REV1 11The output mode “Single 16-bit 555 Pixel Per Clock” is shown in Figure 4. In this mode, each SPCLK will clock outa single pixel, with

12 AN269REV1AN269The output mode “2-2/3 Pixels Per Clock” is shown in Figures 5, 6, and 7. Since this mode is rather complex, onediagram shows data du

AN269AN269REV1 13In the second SPCLK for 2-2/3 mode, pixel 2’s Red component will be clocked out of P[0]. All of the Red, Green,and Blue components of

14 AN269REV1AN269In the third SPCLK for 2 2/3 mode, pixel 5’s Green and Red components will be clocked out of P[1:0]. All of the Red,Green, and Blue c

AN269AN269REV1 15In “4 Pixels-Per-Shift-Clock mode“, shown in Figure 8, only 1 bit (the MSB) will be available for the Blue and Greencomponents of the

16 AN269REV1AN2696. SETTING UP DISPLAY TIMING6.1 HSYNC/VSYNC-Style DisplaysIn displays using a HSYNC/VSYNC-style timing interface, the following contr

AN269AN269REV1 17HSYNCSPCLKBLANKtVSYNCtHACTIVEVCSYNCtHSYNCtDCLKSingle Horizontal LineDATAHSYNCSingle Video FrametVACTIVEBLANKBack Porch Interval tHBAC

18 AN269REV1AN2696.1.1 Pixel Data Clock Rate and HClkTotal/VLinesTotalThe pixel clock rate VIDCLK can be determined from the total number of VIDCLK pe

AN269AN269REV1 196.1.2 Horizontal Alignment Signals Timings for a single horizontal line can be seen in Figure 10. To determine when these signals bec

2 AN269REV1AN2693. GENERATION OF THE VIDEO CLOCK, VIDCLKThe internal video clock (VIDCLK), which drives the raster engine and the external pixel clock

20 AN269REV1AN269Next we will determine the appropriate time for the HSYNC signal to become active. As can be seen fromthe diagram, it should become a

AN269AN269REV1 21The next two values of interest for a horizontal line are the times at which active data should be clockedout. These values determine

22 AN269REV1AN2696.1.3 Vertical Alignment SignalsTimings for a single vertical frame can be seen in Figure 12. The timing of the synchronization signa

AN269AN269REV1 23then counts down by 1 for each HSYNC time period, regardless of whether SPCLK/DATA is present ornot. When the counter reaches 0, it i

24 AN269REV1AN269The next two values of interest for a frame are the point at which active data should be clocked out. Thesevalues determine when vali

AN269AN269REV1 25A timing diagram for this type of display is shown in Figure 14. Signal and timing names are those of thecorresponding EP93xx pins. A

26 AN269REV1AN269HSYNCSPCLKtVCSYNCVCSYNCtHSYNCHSingle Horizontal LineDATAHSYNCSingle Video FrameSPCLKOne SPCLK per Horizontal PixelFirst LineVCSYNC(Ho

AN269AN269REV1 276.2.1 VIDCLK and Pixel Data Clock RateFor Frame Type 1 data displays, the SPCLK will be gated such that clock pulses only occur durin

28 AN269REV1AN269Note that the number of available video clocks can also be derived by adding up the number of clocks ineach region, but this approach

AN269AN269REV1 29.HSYNCSPCLKtHSYNCHSingle Horizontal LineDATAOne SPCLK per Horizontal PixelVCSYNC(HorizontalLine 1 ONLY)tSPCLKtHSYNCLtHSYNCSPCLKtSPCLK

AN269AN269REV1 3/* Desired SPCLK frequency is passed in as "freq" */int ep93xx_set_video_div(unsigned long freq){/* pdiv, div, psel and esel

30 AN269REV1AN269Since the remaining region widths are determined by their respective timing parameters, here are someequations to determine the numbe

AN269AN269REV1 316.2.3 Vertical Alignment SignalsThe vertical timing alignment signals are easily determined by looking at Figure 17.The total number

32 AN269REV1AN269Another result of having no “blank” lines is that the active region covers all of the horizontal lines, so theactive region is the en

AN269AN269REV1 33A timing diagram for this type of display is shown in Figure 18. Signal and timing names are those of thecorresponding EP93xx pins. A

34 AN269REV1AN269HSYNCSPCLKtVCSYNCVCSYNCtHSYNCHSingle Horizontal LineDATAHSYNCSingle Video FrameSPCLKOne SPCLK per Horizontal PixelFirst LineVCSYNC(Ho

AN269AN269REV1 356.3.1 VIDCLK and Pixel Data Clock RateFor a frame type 2 data display, the SPCLK will be gated such that clock pulses only occur duri

36 AN269REV1AN2696.3.2 Horizontal Alignment SignalsTo determine the length of time spent on a single horizontal line, the refresh rate is multiplied b

AN269AN269REV1 37Now, the number of VIDCLK periods required for the active region (i.e., region with valid pixel data) canbe determined. In the follow

38 AN269REV1AN269that the timing is met by making the quantity larger than it needs to be. The time from the last SPCLK untilthe VCSYNC signal becomes

AN269AN269REV1 39Since the remaining region widths are determined by their respective timing parameters, here are someequations to determine the numbe

4 AN269REV1AN2694. USING THE HORIZONTAL AND VERTICAL COUNTER FOR TIMING-SIGNAL GENERATIONConceptually, all timing synchronization outputs from the EP9

40 AN269REV1AN2696.3.3 Vertical Alignment SignalsThe vertical timing alignment signals are easily determined by looking at Figure 21.The total number

AN269AN269REV1 41Note that VActiveStop is set such that data will never be stopped due to vertical position. Also, the SPCLKshould not be stopped due

42 AN269REV1AN2697. GRAYSCALE LOOK-UP TABLESEach of the Red, Green, and Blue outputs from either the color look-up table (LUT) or data directly from m

AN269AN269REV1 43** Global Data:* |>I | O | IO<|, |>dataname<|*** END_FUNC *******************************************************

44 AN269REV1AN269 int start_position)/* Description:* This allows a small range of LUT entries to be replaced.*** Exception Handling (if a

AN269AN269REV1 45Here is the Red grayscale LUT, in the order as would be seen in the EP93xx User’s Guide table “GrayscaleLook-Up Table (GrySclLUT)”. N

46 AN269REV1AN269As mentioned in the EP93xx User’s Guide, each pixel from the frame buffer may go through the color LUT,followed by the grayscale LUT,

AN269AN269REV1 47The interpretation of this diagram is simple. For the first video frame, if the color Red[7:5] = 001b covers theentire screen, then t

48 AN269REV1AN269For the case of Red[7:5] = 011b, the following output patterns will be generated:For this pixel input value, the pixel output value i

AN269AN269REV1 49To edit the entries in the grayscale LUT, the first step is to create the pixel pattern for each frame. As notedin the EP93xx User’s

AN269AN269REV1 5When the output of the horizontal down counter rolls over, it will decrement the vertical down counter at one countper horizontal line

50 AN269REV1AN269Table entries that are don’t cares (indicated by gray shading) are written as 0, but can be written as 1. If thepixel value of 010b f

AN269AN269REV1 518. RASTER MEMORY BUS BANDWIDTH CALCULATIONSince the raster engine uses the main memory of the EP93xx, the total memory bandwidth shou

52 AN269REV1AN269Appendix A: Example HSYNC/VSYNC-Style LCD Display - LG/Philips’s LB064V02-B1The display used in this example is an LG/Philips LB064V

AN269AN269REV1 53values of 2, 2.5, and 3. This yields possible values of VDIV. Using those values as PDIV and VDIV, we can computethe error in VIDCLK

54 AN269REV1AN269HActiveStop = HBlankStopHActiveStop = 22Since no clock gating is required, the HClkStart should be set to HClkTotal and HClkStop shou

AN269AN269REV1 55The output mode for this display (taken from table “Output Pixel Transfer Modes“ in the Raster section of the EP93xxUser’s Guide) is

56 AN269REV1AN269Appendix B:Example Frame Type 1 Display - Kyocera’s KCS057QV1AJ-G20For this section, we will be using the Kyocera KCS057QV1AJ-G20 3-c

AN269AN269REV1 57Once the VIDCLKDIV register has been setup, the actual VIDCLK rate can be used for setting up the horizontalLOAD/HSYNC pulse timing.

58 AN269REV1AN269The output mode for this display is 2-2/3 mode, and can be seen in Figures 5, 6, and 7, which yields the connectionsshown in Table 18

AN269AN269REV1 59Appendix C:Example 4-BIT STN-Style LCD DisplayThe display used in this example is monochrome STN LCD display as HOSIDEN HLAM6323. The

6 AN269REV1AN269Figure 2. Offset for HSync, HActive, VSync and HCLKHSync and Blank must be raised high after the last byte of data is transferred.Fin

60 AN269REV1AN269The first step in setting up the EP93XX raster engine for this display involves determining the proper SPCLK rate. Using the followin

AN269AN269REV1 61Next, the Horizontal Synchronization Signals can be determined, using the following equations:HClkTotal = tHORIZ - 1HClkTotal = 90 -

62 AN269REV1AN269Figure 24. HOSIDEN HLAM6323 Signal Timing in an EP93xx System(PIXMODE = 0x1401 - 4 Bits per Pixel)Table 20. EP93xx to HOSIDEN HLAM63

AN269AN269REV1 63C.1 Frame Buffer Organization, 1 Bit per Pixel, 320 x 240Figure 25. Frame Buffer Organization for HOSIDEN HLAM6323(1 bit per Pixel,

64 AN269REV1AN269C.2 Reference Schematic for HOSIDEN HLAM6323 in an EP93xx System5V_D05V_D15V_D25V_D35V_FRAME5V_M5V_CL15V_CL25V_DOFFGNDVEE(-20V)12Jump

AN269AN269REV1 65Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one neare

AN269AN269REV1 7The Calculations for HClksTotal areHClksTotal = Number of Horizontal Clocks - 1= 20 -1= 19The Calculations for HSyncStart areHSyncStar

8 AN269REV1AN269The Calculations for HClkStrt areHClkStrt = HClkstotal - Offset of HClk = 19 - 6 = 13The Calculations for HClkStop areHClkStop = HClks

AN269AN269REV1 95. GENERAL DESCRIPTION OF PIXEL OUTPUT MODESEach display type specifies the number of bits (and therefore bits per color) clocked out