Cirrus-logic CS5463 Manuel d'utilisateur

Copyright  Cirrus Logic, Inc. 2011(All Rights Reserved)http://www.cirrus.comCS5463Single Phase, Bi-directional Power/Energy ICFeatures Energy Data L

CS546310 DS678F3Notes: 10. All measurements performed under static conditions.11. If a crystal is used, then XIN frequency must remain between 2.5 MHz

CS5463DS678F3 11SWITCHING CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• Ty

CS546312 DS678F3t1t2t3t4t5MSBMSB-1LSBMSBMSB-1LSBMSBMSB-1LSBMSBMSB-1LSBCommand Time 8 SCLKs High Byte Mid Byte Low ByteCSSCLKSDIt10t9RESETSDOSCLKCSLast

CS5463DS678F3 13SWITCHING CHARACTERISTICS (Continued)Notes: 19. Pulse output timing is specified at MCLK = 4.096 MHz, E2MODE = 0, and E3MODE[1:0] = 0.

CS546314 DS678F34. THEORY OF OPERATIONThe CS5463 is a dual-channel analog-to-digital convert-er (ADC) followed by a computation engine that per-forms

CS5463DS678F3 15provides a pulse output that is proportional to the reac-tive power or apparent power. Output E3 can also be setto display the sign of

CS546316 DS678F35. FUNCTIONAL DESCRIPTION5.1 Analog InputsThe CS5463 is equipped with two fully differential inputchannels. The inputs VIN and IIN

CS5463DS678F3 17for unsigned registers is a normalized value between 0and 1. A register value ofrepresents the maximum possible value.At each instanta

CS546318 DS678F3The pulse output frequency of E1 is directly proportionalto the active power calculated from the input signals. Tocalculate the output

CS5463DS678F3 19Output pin E3 is high when the line voltage is positiveand pin E3 is low when the line voltage is negative.5.5.5 PFMON Output ModeSet

CS54632 DS678F3TABLE OF CONTENTS1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CS546320 DS678F3The temperature update rate is a function of the numberof ADC samples. With MCLK = 4.096 MHz and K = 1the update rate is:The Cycle Cou

CS5463DS678F3 21drive the device from an external clock source, XOUTshould be left unconnected while XIN is driven by theexternal circuitry. There is

CS546322 DS678F3If the serial port interface becomes unsynchronized withrespect to the SCLK input, any attempt to clock validcommands into the serial

CS5463DS678F3 235.16 CommandsAll commands are 8 bits in length. Any command byte value that is not listed in this section is invalid. Commands that

CS546324 DS678F35.16.5 Register Read/Write The Read/Write informs the command decoder that a register access is required. During a read operation,

CS5463DS678F3 25Register Page 1Address RA[4:0] Name Description0 00000 PulseWidth Energy Pulse Output Width1 00001 LoadMinNo Load Threshold2 00010 TGa

CS546326 DS678F36. REGISTER DESCRIPTION1. “Default” = bit status after power-on or reset2. Any bit not labeled is Reserved. A zero should always be

CS5463DS678F3 276.1.2 Current and Voltage DC Offset Register ( IDCoff , VDCoff ) Address: 1 (Current DC Offset); 3 (Voltage DC Offset)Default = 0x00

CS546328 DS678F36.1.6 Instantaneous Current, Voltage, and Power Registers ( I , V , P )Address: 7 (Instantaneous Current); 8 (Instantaneous Voltage);

CS5463DS678F3 296.1.10 Power Offset Register ( Poff )Address: 14 Default = 0x000000Power Offset (Poff) is added to the instantaneous power being acc

CS5463DS678F3 36.1.7 Active (Real) Power Register ( PActive ) . . . . . . . . . . . . . . . . . . . . . . . . . . 286.1.8 RMS Current & Voltage

CS546330 DS678F3lates due to an input above full scale. The level at which the modulator oscillates is significantly higher than the voltage channel’s

CS5463DS678F3 31IHPF (VHPF) Enables the high-pass filter on the current (voltage) channel.0 = High-pass filter disabled (default)1 = High-pass filter

CS546332 DS678F36.1.17 Reactive Power Register ( QTrig )Address: 24 The Reactive Power (QTrig) is calculated using trigonometric identities. (See Se

CS5463DS678F3 336.1.20 Control Register ( Ctrl ) Register Address: 28 Default = 0x000000STOP Terminates the auto-boot sequence.0 = Normal (def

CS546334 DS678F36.1.23 Fundamental Reactive Power Register ( QH )Address: 31 (read only)Fundamental Reactive Power (QH) is calculated by performing

CS5463DS678F3 356.2 Page 1 Registers6.2.1 Energy Pulse Output Width ( PulseWidth )Address: 0 Default = 1PulseWidth sets the duration of energy puls

CS546336 DS678F36.3 Page 3 Registers6.3.1 Voltage Sag and Current Fault Duration Registers ( VSAGDuration , ISAGDuration )Address: 6 (Voltage Sag Du

CS5463DS678F3 377. SYSTEM CALIBRATION7.1 Channel Offset and Gain CalibrationThe CS5463 provides digital DC offset and gain com-pensation that can be

CS546338 DS678F3each instantaneous measurement to nullify the DCcomponent present in the system during conversioncommands.7.1.2.2 AC Offset Calibrati

CS5463DS678F3 39However, an AC signal cannot be used for DC gain cal-ibration.7.1.3.2 DC Gain Calibration SequenceInitiate a DC gain calibration. The

CS54634 DS678F3 LIST OF FIGURESFigure 1. CS5463 Read and Write Timing Diagrams... 12Fig

CS546340 DS678F38. AUTO-BOOT MODE USING E2PROMWhen the CS5463 MODE pin is asserted (logic 1), theCS5463 auto-boot mode is enabled. In auto-boot mode,t

CS5463DS678F3 419. BASIC APPLICATION CIRCUITSFigure 18 shows the CS5463 configured to measurepower in a single-phase, 2-wire system while operatingin

CS546342 DS678F3VA+ VD+CS54630.1 µF470 µF500470 nF500NR3R4RBurden1014VIN+9VIN-IIN-101615IIN+PFMONCPUCLKXOUTXINOptionalClockSourceRESET172124CSSDSDO

CS5463DS678F3 43VA+ VD+0.1 µF470 µF1k235 nF500R1R21014VIN+9VIN-IIN-101615IIN+PFMONCPUCLKXOUTXINOptionalClockSourceRESET172124CSSDISDOSCLKINT0.1 µFV

CS546344 DS678F310.PACKAGE DIMENSIONSNotes: 3. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold m

CS5463DS678F3 4511. ORDERING INFORMATION 12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specified

CS546346 DS678F313. REVISION HISTORY Revision Date ChangesA1 MAR 2005 Advance ReleasePP1 AUG 2005 First preliminary release.F1 NOV 2005 First final re

CS5463DS678F3 51. OVERVIEWThe CS5463 is a CMOS monolithic power measurement device with a computation engine and an ener-gy-to-frequency pulse output.

CS54636 DS678F32. PIN DESCRIPTIONClock GeneratorCrystal OutCrystal In1,24XOUT, XIN – The output and input of an inverting amplifier. Oscillation occu

CS5463DS678F3 73. CHARACTERISTICS & SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSANALOG CHARACTERISTICS• Min / Max characteristics and specificat

CS54638 DS678F3ANALOG CHARACTERISTICS (Continued)Notes: 3. Applies before system calibration.4. All outputs unloaded. All inputs CMOS level.5. Measure

CS5463DS678F3 9VOLTAGE REFERENCENotes: 8. The voltage at VREFOUT is measured across the temperature range. From these measurements the following formu