Cirrus-logic CS53L21 Manuel d'utilisateur télécharger pdf (Page 15)

DS700PP1 15

CS53L21

7. After powering up the CS53L21, RESET should be held low after the power supplies and clocks are

settled.

8. See “Example System Clock Frequencies” on page 57 for typical MCLK frequencies.

9. See“Master” on page 30.

10. “MCLK” refers to the external master clock applied.

Master Mode (Note 9)

Output Sample Rate (LRCK) All Speed Modes

(Note 10)

-Hz

LRCK Duty Cycle

45 55 %

SCLK Frequency

1/t

- 64•F

SCLK Duty Cycle

45 55 %

LRCK Edge to SDOUT MSB Output Delay

d(MSB)

-52ns

SDOUT Setup Time Before SCLK Rising Edge

s(SDO-SK)

20 - ns

SDOUT Hold Time After SCLK Rising Edge

h(SK-SDO)

30 - ns

Parameters Symbol Min Max Units

MCLK

128

-----------------

h(SK-SDO)

MSB MSB-1

LRCK

SCLK

SDOUT

d(MSB)

s(LK-SK)

s(SDO-SK)

Figure 3. Serial Audio Interface Slave Mode Timing

h(SK-SDO)

MSB MSB-1

LRCK

SCLK

SDOUT

d(MSB)

s(SDO-SK)

Figure 4. Serial Audio Interface Master Mode Timing

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 65 66

Commentaires sur ces manuels

Pas de commentaire

Cirrus-logic CS53L21 Manuel d'utilisateur Page 15

Commentaires sur ces manuels

Produits connexes et manuels pour Matériel Cirrus-logic CS53L21