Cirrus-logic CS5376A Manuel d'utilisateur

Copyright © Cirrus Logic, Inc. 2008(All Rights Reserved)http://www.cirrus.comCS5376ALow-power, Multi-channel Decimation FilterFeaturesz 1- to 4-channe

CS5376ADS612F4 10Microcontroller Boot Configuration CommandsEEPROM Boot Configuration Commands[DATA] indicates data word returned from digital filter.

CS5376A100 DS612F423.2.14 VERSION : 0x2E (MSB) 23 22 21 20 19 18 17 16TYPE7 TYPE6 TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0R/WR/WR/WR/WR/WR/WR/WR/W0111

CS5376ADS612F4 10123.2.15 SELFTEST : 0x2F (MSB) 23 22 21 20 19 18 17 16-- -- -- -- EU3 EU2 EU1 EU0R/WR/WR/WR/WR/WR/WR/WR/W0000101015 14 13 12 11

CS5376ADS612F4 10224.PIN DESCRIPTIONSTIMEBCLKSYNCSDDATSDRDYSDCLKSDTKOSDTKITRSTTMSTCKTDITDOGNDVDTBSCLKTBSDATADNCVDD2MCLK/2MCLKMSYNCMDATA4MFLAG4MDATA3MF

CS5376ADS612F4 103Pin NamePin NumberPin TypePin DescriptionJTAG portTRST1 Input JTAG reset, active low.Connect to GND if JTAG is not used.TMS 2 Input

CS5376A104 DS612F4Clock and SynchronizationCLK 58 Input Clock input, nominal 32.768 MHz.SYNC 59 Input Sync input.Serial Data PortSDDAT 60 Output SD po

CS5376ADS612F4 10525.PACKAGE DIMENSIONSINCHES MILLIMETERSDIM MIN MAX MIN MAXA --- 0.063 --- 1.60A1 0.002 0.006 0.05 0.15B 0.007 0.011 0.17 0.27D 0.461

CS5376A106 DS612F426.ORDERING INFORMATION 27.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specified b

CS5376ADS612F4 11Bits 23:20 19:16 15:12 11:8 7:4 3:0Selection 0000 0000 IIR2 IIR1 FIR2 FIR1Figure 3. FIR and IIR Coefficient Set Selection WordBits 1

CS5376ADS612F4 12SPI 1 RegistersDigital Filter RegistersName Addr. Type # Bits DescriptionSPI1CTRL 00 - 02 R/W 8, 8, 8 SPI 1 ControlSPI1CMD 03 - 05 R/

CS5376ADS612F4 132. CHARACTERISTICS AND SPECIFICATIONS• Min / Max characteristics and specifications are guaranteed over the Specified Operating Condi

CS5376ADS612F4 14THERMAL CHARACTERISTICS DIGITAL CHARACTERISTICS Notes: 2. Max leakage for pins with pull-up resistors (TRST, TMS, TDI, SSI, GPIO, MOS

CS5376ADS612F4 15SWITCHING CHARACTERISTICS SPI 1 Interface Timing (External Master)Parameter Symbol Min Typ Max UnitMOSI Write TimingSSI Enable to Va

CS5376ADS612F4 16SWITCHING CHARACTERISTICS Serial Data Port (SD Port)Parameter Symbol Min Typ Max UnitSDTKI to SDRDY Falling Edge t160 - - nsSDTKI Hi

CS5376ADS612F4 17SWITCHING CHARACTERISTICS CLK, SYNC, MCLK, MSYNC, and MDATAxNotes: 3. Master clock frequencies above or below 32.768 MHz will affect

CS5376ADS612F4 18SWITCHING CHARACTERISTICS Test Bit Stream (TBS)5. TBSCLK phase can be delayed in 1/8 increments. The timing diagram shows no TBSCLK d

CS5376ADS612F4 193. SYSTEM DESIGN WITH CS5376AFigure 9 illustrates a simplified block diagram ofthe CS5376A in a multi-channel measurement sys-tem.Up

CS5376ADS612F4 2TABLE OF CONTENTS1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.1. Digital F

CS5376A20 DS612F43.3 Clock GenerationA single 32.768 MHz low-jitter clock input, whichcan be generated from a VCXO based PLL, is re-quired to drive th

CS5376ADS612F4 214. POWER SUPPLIESThe CS5376A has three sets of power supply in-puts. Two sets supply power to the I/O pins of thedevice (VDD1, VDD2),

CS5376A22 DS612F4VD, GND - Pins 7, 40, 6, 23, 39Sets the operational voltage of the CS5376A logiccore. Can be driven with voltages from 3 V to 5 V.A 3

CS5376ADS612F4 235. RESET CONTROLThe CS5376A reset signal is active low. When re-leased, a series of self-tests are performed and thedevice either act

CS5376A24 DS612F46. CLOCK GENERATIONThe CS5376A requires a 32.768 MHz master clockinput, which is used to generate internal digital fil-ter clocks and

CS5376ADS612F4 257. SYNCHRONIZATIONThe CS5376A has a dedicated SYNC input thataligns the internal digital filter phase and generatesan external signal

CS5376A26 DS612F48. CONFIGURATION BY EEPROM After reset, the CS5376A reads the state of theBOOT pin to determine a source for configurationcommands. I

CS5376ADS612F4 27SCK1MOSIEECSMSB LSBMISOX612345MSB LSB61234518276543CycleMOSIMISOSSI0x03 ADDRDATA1 DATA3DATA2EECSREAD1 BYTE / 3 BYTEADDRCMDADDRDATA2 B

CS5376A28 DS612F45 KByte (40 Kbit), which includes command over-head: Supported serial configuration EEPROMs areSPI mode 0 (0,0) compatible, 16-bit a

CS5376ADS612F4 29Sample Command:Write IIR1 coefficients 0x84BC9D, 0x7DA1B1,0x825E4F, and IIR2 coefficients 0x83694F,0x3CAD5F, 0x3E5104, 0x835DF8, 0x3E

CS5376ADS612F4 39.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329.2. Microcontroller Ha

CS5376A30 DS612F4Sample Command:Write test bit stream data 0x000000, 0x0007DA,0x000FB5, 0x00178F. 05 00 00 04 00 00 00 00 07 DA 00 0F B5 00 17 8

CS5376ADS612F4 31Table 6. Example EEPROM FileAddr Data Description00 00 Mfg header01 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E

CS5376A32 DS612F49. CONFIGURATION BY MICROCONTROLLERAfter reset, the CS5376A reads the state of theBOOT pin to determine a source for configurationcom

CS5376ADS612F4 33SCK1MOSIFigure 18. Microcontroller Serial TransactionsSSIMSB LSBMISOX612345MSB LSB61234518276543CycleMOSI 0x02 ADDR Data1MISOMOSIMIS

CS5376A34 DS612F49.3.2 SPI 1 registersThe SPI 1 registers are shown in Figure 19 and are24-bit registers mapped into an 8-bit register spaceas high, m

CS5376ADS612F4 35The E2DREQ bit reads high while a configurationcommand is being processed. When low, the digitalfilter is ready to receive a new conf

CS5376A36 DS612F4 Delay 1 ms, monitor SINT, or poll E2DREQ MOSI: 03 06 00 00 00 MISO: xx xx 07 04 31 02 03 00 00 02 00 00 20 Delay 1 ms

CS5376ADS612F4 37on page 64 for information about using custom testbit stream data sets.Sample Command:Write test bit stream data 0x000000, 0x0007DA,0

CS5376ADS612F4 38Table 8. Example Microcontroller ConfigurationTransaction SPI Data Description01 02 03 00 00 05 00 22 00 Write ROM coefficients02 De

CS5376ADS612F4 3910.MODULATOR INTERFACEThe CS5376A performs digital filtering for up tofour ∆Σ modulators. Signals from the modulatorsare connected th

CS5376ADS612F4 417.7. TBS Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6618. Time Break Controller. .

CS5376A40 DS612F410.4Modulator Data InputsThe MDATA input expects 1-bit ∆Σ data at a512 kHz or 256 kHz rate. The input rate is selectedby a bit in the

CS5376ADS612F4 4111.DIGITAL FILTER INITIALIZATIONThe CS5376A digital filter consists of three multi-stage sections: a three stage SINC filter, a two s

CS5376A42 DS612F411.2.2 Output Word RateThe CS5376A digital filter supports output wordrates (OWRs) between 4000 SPS and 1 SPS. Theoutput word rate is

CS5376ADS612F4 4312.SINC FILTERThe SINC filters primary purpose is to attenuateout-of-band noise components from the ∆Σ modu-lators. While doing so, t

CS5376ADS612F4 44SINC1 – Single stage, fixed decimate by 8 5th order decimate by 8, 36 coefficients SINC2 – Multi-stage, variable decimation Stage

CS5376ADS612F4 45Filter Type System Function Filter Coefficients SINC2 (Stage 1) SINC2 (Stage 2) 4th order decimate by 2 5 coefficients 41211)(⎟⎟⎠⎞

CS5376ADS612F4 46Filter Type System Function Filter Coefficients SINC3 (Stage 1) SINC3 (Stage 2) SINC3 (Stage 3) 4th order decimate by 5 17 coeffici

CS5376ADS612F4 4713.FIR FILTERThe finite impulse response (FIR) filter block con-sists of two cascaded stages, FIR1 and FIR2. Itcompensates for SINC f

CS5376A48 DS612F413.4Programmable FIR CoefficientsA maximum of 255 + 255 coefficients can be pro-grammed into FIR1 and FIR2 to create a customfilter r

CS5376ADS612F4 49FIR1 – Single stage, fixed decimate by 4 Coefficient set 0: linear phase decimate by 4, 48 coefficients Coefficient set 1: minimum p

CS5376ADS612F4 5Figure 14. EEPROM Configuration Block Diagram . . . . . . . . . . . . . . . . . . . . . .26Figure 15. SPI 1 EEPROM Read Transaction

CS5376ADS612F4 50Individual filter stage group delay (no IIR) Decimation Ratios Number of Coefficients Group Delay (Filter Stage Input Rate) SINC1 8

CS5376ADS612F4 51Minimum phase group delay FIR1 Minimum Phase Group Delay (Normalized frequency) FIR2 Minimum Phase Group Delay (Normalized freque

CS5376ADS612F4 52Filter Type Filter Coefficients (normalized 24-bit) FIR1 (Coefficient set 0) Low pass, SINC compensation Linear phase decimate by 4

CS5376ADS612F4 53Filter Type Filter Coefficients (normalized 24-bit) FIR2 (Coefficient set 0) Low pass, passband to 40% fs Linear phase decimate by 2

CS5376ADS612F4 54Filter Type Filter Coefficients (normalized 24-bit) FIR2 (Coefficient set 1) Low pass, passband to 40% fs Minimum phase decimate by

CS5376ADS612F4 5514.IIR FILTERThe infinite impulse response (IIR) filter blockconsists of two cascaded stages, IIR1 and IIR2. Itcreates a high-pass co

CS5376A56 DS612F4characteristic equations model the operation of the2nd order IIR filter with unnormalized coefficients.W5 = W4W4 = W3W3 = X + (-a21 *

CS5376ADS612F4 57IIR1 – Single stage, no decimation 1st order no decimation, 3 coefficients Coefficient set 0: high-pass, corner 0.15% fs (3 Hz at 2

CS5376A58 DS612F4Filter Type System Function Filter Coefficients (normalized 24-bit) IIR1 (Coefficient set 0) 1st order, high pass Corner at 0.15% f

CS5376ADS612F4 5915.GAIN AND OFFSET CORRECTIONThe CS5376A digital filter can apply independentgain and offset corrections to the data of each mea-sure

CS5376ADS612F4 6LIST OF TABLESTable 1. Microcontroller and EEPROM Configuration Commands. . . . . . . . . . .10Table 2. TBS Configurations Using On-

CS5376A60 DS612F4value in the OFFSETx registers (0x25-0x28) fromthe digital filter output data word.Offset correction values are 24-bit two’s comple-m

CS5376ADS612F4 6116.SERIAL DATA PORTOnce digital filtering is complete, each 24-bit out-put sample is combined with an 8-bit status byte.These 32-bit

CS5376A62 DS612F4BRK digital filter register (0x29) programs thesample delay for the TB bit output. See “TimeBreak Controller” on page 67 for more inf

CS5376ADS612F4 63data is read from the SD port data FIFO, SDRDY isreleased and SDTKO is pulsed high for 100 nS.16.3.2 Continuous ModeTo have the CS537

CS5376A64 DS612F417.TEST BIT STREAM GENERATORThe CS5376A test bit stream (TBS) generator cre-ates sine wave ∆Σ bit stream data to drive an exter-nal t

CS5376ADS612F4 65Loopback - LOOPEnables digital loopback from the TBS output tothe MDATA inputs.Run - RUNEnables the test bit stream generator.Data De

CS5376A66 DS612F4set can be written into the CS5376A. The numberof data points to write, up to a maximum of 1024,depends on the required test signal f

CS5376ADS612F4 6718.TIME BREAK CONTROLLERA time break signal is used to mark timing eventsthat occur during measurement. An external signalsets a flag

CS5376A68 DS612F419.GENERAL PURPOSE I/OThe General Purpose I/O (GPIO) block provides 12general purpose pins to interface with externalhardware.19.1Pin

CS5376ADS612F4 69Any GPIO pin can be used as an open-drain outputby setting the data value to 0, enabling the pull-up,and using the GP_DIR direction b

CS5376ADS612F4 71. GENERAL DESCRIPTIONThe CS5376A is a multi-channel digital filter withintegrated system peripherals. Figure 1 illustrates asimplifie

CS5376A70 DS612F420.SERIAL PERIPHERAL INTERFACE 2The Serial Peripheral Interface 2 (SPI 2) port is amaster mode SPI port designed to interface with se

CS5376ADS612F4 7120.3.1 SPI 2 Control RegisterThe SPI 2 hardware is configured by theSPI2CTRL digital filter register (0x10). Bits in this register se

CS5376A72 DS612F4During a transaction, bits in SPI2CMD are outputMSB first, with data in SPI2DAT written or readfollowing.20.3.3 SPI 2 Data RegisterTh

CS5376ADS612F4 73SPI modes 1 and 4 work similarly to modes 0 and3, with the serial clock defined to have data valid onfalling edges and transitioning

CS5376ADS612F4 74SCK2SOFigure 39. SPI 2 Transaction DetailsCSMSB LSBSCK2SISCKPO = 0SCKPO = 1X612345LSBMSB 6 1234518276543CycleSlave devices only driv

CS5376ADS612F4 7521.BOUNDARY SCAN JTAGThe CS5376A includes an IEEE 1149.1 boundary scan JTAG port to test PCB interconnections. Refer tothe IEEE 1149.

CS5376A76 DS612F421.2.1 JTAG ResetAs required by the IEEE 1149.1 specification, theJTAG TRST signal is independent of the CS5376ARESET signal. In syst

CS5376ADS612F4 77BRC Pin Function BRC Pin Function BRC Pin Function1 TBSCLK data out 36 GPIO3 data in 68 GPIO11 data in2 TBSDATA data out 37 data out

CS5376ADS612F4 7822.DEVICE REVISION HISTORYThe CS5376A is a pin compatible upgrade to theCS5376. The part family has had three revisions:CS5376 rev AC

CS5376ADS612F4 79Modified SINC2 filter to correct gain andtiming errorsCorrected SINC2 decimate by 2 gain errorwhich affected 4000 SPS operation. Also

CS5376A8 DS612F4• Digital offset correction and calibration.- Individual channel offset correction to re-move measurement offsets.- Calibration engine

CS5376A80 DS612F4Added Test Bit Stream (TBS) synchroniza-tion in sine wave mode.The TBS sine wave phase will reset if bit 11 ofthe TBSCFG register is

CS5376ADS612F4 8123.REGISTER SUMMARY23.1SPI 1 RegistersThe CS5376A SPI 1 registers interface the serial port to the digital filter.Name Addr. Type # B

CS5376A82 DS612F423.1.1 SPI1CTRL : 0x00, 0x01, 0x02 (MSB) 23 22 21 20 19 18 17 16-- -- -- -- -- -- -- --R/W R/W1 R/W R/W R/W R/W R/W R/W000010111

CS5376ADS612F4 8323.1.2 SPI1CMD : 0x03, 0x04, 0x05 (MSB) 23 22 21 20 19 18 17 16S1CMD23 S1CMD22 S1CMD21 S1CMD20 S1CMD19 S1CMD18 S1CMD17 S1CMD16R/

CS5376A84 DS612F423.1.3 SPI1DAT1 : 0x06, 0x07, 0x08 (MSB) 23 22 21 20 19 18 17 16S1DAT23 S1DAT22 S1DAT21 S1DAT20 S1DAT19 S1DAT18 S1DAT17 S1DAT16R

CS5376ADS612F4 8523.1.4 SPI1DAT2 : 0x09, 0x0A, 0x0B (MSB) 23 22 21 20 19 18 17 16S1DAT23 S1DAT22 S1DAT21 S1DAT20 S1DAT19 S1DAT18 S1DAT17 S1DAT16R

CS5376A86 DS612F423.2 Digital Filter RegistersThe CS5376A digital filter registers control hardware peripherals and filtering functions.Name Addr. Typ

CS5376ADS612F4 8723.2.1 CONFIG : 0x00(MSB)2322212019181716-- -- -- -- -- DFS2 DFS1 DFS0R/W R/W R/W R/W R/W R/W R/W R/W0000010115 14 13 12 11 10 9 8--

CS5376A88 DS612F423.2.2 GPCFG0 : 0x0E (MSB) 23 22 21 20 19 18 17 16GP_DIR7 GP_DIR6 GP_DIR5 GP_DIR4 GP_DIR3 GP_DIR2 GP_DIR1 GP_DIR0R/WR/WR/WR/WR/W

CS5376ADS612F4 8923.2.3 GPCFG1 : 0x0F (MSB) 23 22 21 20 19 18 17 16-- -- -- --GP_DIR11 GP_DIR10 GP_DIR9 GP_DIR8R/W R/W R/W R/W R/W R/W R/W R/W000

CS5376ADS612F4 9- 37 mW for 4-channel operation at 500 SPS(9.25 mW/channel).-40µW standby mode.• Flexible power supply configurations.- Separate digit

CS5376A90 DS612F423.2.4 SPI2CTRL : 0x10(MSB) 23 22 21 20 19 18 17 16WOM SCKFS2 SCKFS1 SCKFS0 SPI2EN3 SPI2EN2 SPI2EN1 SPI2EN0R/WR/WR/WR/WR/WR/WR/WR/W00

CS5376ADS612F4 9123.2.5 SPI2CMD : 0x11 (MSB) 23 22 21 20 19 18 17 16-- -- -- -- -- -- -- --R/W R/W R/W R/W R/W R/W R/W R/W0000000015 14 13 12 11

CS5376A92 DS612F423.2.6 SPI2DAT : 0x12 (MSB) 23 22 21 20 19 18 17 16SDAT23 SDAT22 SDAT21 SDAT20 SDAT19 SDAT18 SDAT17 SDAT16R/WR/WR/WR/WR/WR/WR/WR

CS5376ADS612F4 9323.2.7 FILTCFG : 0x20 (MSB) 23 22 21 20 19 18 17 16-- -- -- EXP4 EXP3 EXP2 EXP1 EXP0R/WR/WR/WR/WR/WR/WR/WR/W0000000015 14 13 12

CS5376A94 DS612F423.2.8 GAIN1 - GAIN4 : 0x21 - 0x24 (MSB) 23 22 21 20 19 18 17 16GAIN23 GAIN22 GAIN21 GAIN20 GAIN19 GAIN18 GAIN17 GAIN16R/WR/WR/W

CS5376ADS612F4 9523.2.9 OFFSET1 - OFFSET4 : 0x25 - 0x28 (MSB) 23 22 21 20 19 18 17 16OFST23 OFST22 OFST21 OFST20 OFST19 OFST18 OFST17 OFST16R/WR/

CS5376A96 DS612F423.2.10 TIMEBRK : 0x29 (MSB) 23 22 21 20 19 18 17 16TBRK23 TBRK22 TBRK21 TBRK20 TBRK19 TBRK18 TBRK17 TBRK16R/WR/WR/WR/WR/WR/WR/W

CS5376ADS612F4 9723.2.11 TBSCFG : 0x2A (MSB) 23 22 21 20 19 18 17 16INTP7 INTP6 INTP5 INTP4 INTP3 INTP2 INTP1 INTP0R/WR/WR/WR/WR/WR/WR/WR/W000000

CS5376A98 DS612F423.2.12 TBSGAIN : 0x2B (MSB) 23 22 21 20 19 18 17 16TGAIN23 TGAIN22 TGAIN21 TGAIN20 TGAIN19 TGAIN18 TGAIN17 TGAIN16R/WR/WR/WR/WR

CS5376ADS612F4 9923.2.13 SYSTEM1, SYSTEM2 : 0x2C, 0x2D (MSB) 23 22 21 20 19 18 17 16SYS23 SYS22 SYS21 SYS20 SYS19 SYS18 SYS17 SYS16R/WR/WR/WR/WR/