Cirrus-logic CS5346 Manuel d'utilisateur

Copyright  Cirrus Logic, Inc. 2012 (All Rights Reserved)Preliminary Product InformationThis document contains information for a product under develop

10 DS861PP3CS5346ANALOG CHARACTERISTICS CONT.6. Referred to the typical A/D Full-Scale Input Voltage.Parameter Symbol Min Typ Max UnitLine-Level Input

DS861PP3 11CS5346DIGITAL FILTER CHARACTERISTICS 7. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 1

12 DS861PP3CS5346DC ELECTRICAL CHARACTERISTICSAGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode.9. Power

DS861PP3 13CS5346DIGITAL INTERFACE CHARACTERISTICSTest conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 3.3 V.11. Serial Port s

14 DS861PP3CS5346SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTLogic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VLS, CL = 20 pF. (Note 12)12. See Figure 1 an

DS861PP3 15CS5346 slrtSDOUTSCLKOutputLRCKOutputsdotslrtSDOUTSCLKInputLRCKInputsdotsclkhtsclkltsclkwtFigure 1. Master Mode Serial Aud

16 DS861PP3CS5346SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMATInputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL=30pF.13. Data must be hel

DS861PP3 17CS5346SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL=30pF.14. Data must be he

18 DS861PP3CS53464. TYPICAL CONNECTION DIAGRAMVLS0.1 µF+3.3Vto +5VDGNDVLC0.1 µF+3.3Vto +5VSCL/CCLKSDA/CDOUTAD1/CDINRST2 kSee Note 1AD0/CSNotes:1. Res

DS861PP3 19CS53465. APPLICATIONS5.1 Recommended Power-Up Sequence1. Hold RST low until the power supply, MCLK, and LRCK are stable. In this state, the

2 DS861PP3CS5346TABLE OF CONTENTS1. PIN DESCRIPTIONS - CS5346 ...

20 DS861PP3CS53465.2.2 Master ModeAs a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from MCLK with LRCK e

DS861PP3 21CS53465.4 Analog Input Multiplexer, PGA, and Mic GainThe CS5346 contains a stereo 6-to-1 analog input multiplexer followed by a programmabl

22 DS861PP3CS5346demonstrates a simple solution. The 1800 pF capacitors in the low-pass filter should be C0G or equivalentto avoid distortion issues.5

DS861PP3 23CS53465.6 PGA Auxiliary Analog OutputThe CS5346 includes an auxiliary analog output through the PGAOUT pins. These pins can be configuredto

24 DS861PP3CS5346dress and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT wi

DS861PP3 25CS5346Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown in Figure 16, the write opera

26 DS861PP3CS53465.9 ResetWhen RST is low, the CS5346 enters a low-power mode and all internal states are reset, including the con-trol port and regis

DS861PP3 27CS53466. REGISTER QUICK REFERENCEThis table shows the register names and their associated default values.Addr Function 7 6 5 4 3 2 1 001h C

28 DS861PP3CS53467. REGISTER DESCRIPTION7.1 Chip ID - Register 01hFunction:This register is Read-Only. Bits 7 through 4 are the part number ID, which

DS861PP3 29CS53467.3 ADC Control - Address 04h7.3.1 Functional Mode (Bits 7:6)Function:Selects the required range of sample rates.7.3.2 Digital Interf

DS861PP3 3CS53467.6.1 Channel B PGA Gain (Bits 5:0) ... 307

30 DS861PP3CS53467.4 MCLK Frequency - Address 05h7.4.1 Master Clock Dividers (Bits 6:4)Function:Sets the frequency of the supplied MCLK signal. See Ta

DS861PP3 31CS53467.7 Channel A PGA Control - Address 08h7.7.1 Channel A PGA Gain (Bits 5:0)Function:Sets the gain or attenuation for the ADC input PGA

32 DS861PP3CS53467.8.2 Analog Input Selection (Bits 2:0)Function:These bits are used to select the input source for the PGA and ADC. Please see Table

DS861PP3 33CS53467.10.1 Clock Error (Bit 3)Function:Indicates the occurrence of a clock error condition.7.10.2 Overflow (Bit 1)Function:Indicates the

34 DS861PP3CS53468. PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over th

DS861PP3 35CS53469. FILTER PLOTS Figure 17. Single-Speed Stopband Rejection Figure 18. Single-Speed Stopband RejectionFigure 19. Single-Speed

36 DS861PP3CS5346 Figure 23. Double-Speed Transition Band (Detail) Figure 24. Double-Speed Passband RippleFigure 25. Quad-Speed Sto

DS861PP3 37CS534610.PACKAGE DIMENSIONS11.THERMAL CHARACTERISTICS AND SPECIFICATIONS 1. JA is specified according to JEDEC specifications for multi-l

38 DS861PP3CS534612.ORDERING INFORMATION 13.REVISION HISTORYProduct Description Package Pb-Free Grade Temp Range Container Order #CS534624-bit, 1

4 DS861PP3CS5346LIST OF TABLESTable 1. Speed Modes ...

DS861PP3 5CS53461. PIN DESCRIPTIONS - CS5346 Pin Name # Pin DescriptionSDA/CDOUT 1Serial Control Data (Input/Output) - SDA is a data I/O in I²C® Mode.

6 DS861PP3CS5346AIN1AAIN1B1112Stereo Analog Input 1 (Input) - The full-scale level is specified in the Analog Characteristics specifica-tion table.AGN

DS861PP3 7CS53462. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCESThe CS5346 is p in compatible with the CS5345 and is a drop in replacement for CS5345

8 DS861PP3CS53463. CHARACTERISTICS AND SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSAGND = DGND = 0 V; All voltages with respect to ground.ABSOLUTE M

DS861PP3 9CS5346ANALOG CHARACTERISTICSTest conditions (unless otherwise specified): VA = 5 V; VD = VLS = VLC = 3.3 V; AGND = DGND = 0 V; TA= +25° C; I