Cirrus-logic CS49DV8C Manuel d'utilisateur télécharger pdf (Page 18)

CS49DV8C Data Sheet

32-bit Audio DSP Family

5.13 Switching Characteristics — UART

Figure 7. UART Timing

Parameter Symbol Min Max Unit

UART_CLK period

1. The minimum clock period is limited to DCLKP/32 or the minimum value, whichever is larger.

uclki

266 - ns

UART_CLK duty cycle - 40 60 %

Setup time for UART_RXD t

uckrxsu

Hold time for UART_RXD t

uckrxdv

5-ns

Delay from CLK transition to TXD transition t

ucktxdv

-29ns

UART_CLK

UART_RXD

UART_TXD

uckrxsu

ucktxdv

uckrxdv

ART_TX_EN

txen

txhz

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 29 30

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Cirrus-logic CS49DV8C Manuel d'utilisateur Page 18