Cirrus-logic CS4391A Manuel d'utilisateur télécharger pdf (Page 21)

CS4391A

DS600PP3 21

4.5.5 Freeze (Bit 2)

Function:

This function allows modifications to the registers without the changes being taking effect until Freeze

is disabled. To make multiple changes in the Control port registers take effect simultaneously, set the

Freeze Bit, make all register changes, then Disable the Freeze bit.

4.5.6 Master Clock Divide (Bit 1)

Function:

This function allows the user to select an internal divide by 2 of the Master Clock. This selection is

required to access the higher Master Clock rates as shown in Table 9.

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 39 40

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Cirrus-logic CS4391A Manuel d'utilisateur Page 21