Cirrus-logic CS42L56 Manuel d'utilisateur

Copyright  Cirrus Logic, Inc. 2014(All Rights Reserved)http://www.cirrus.comFEB '14DS851F2Ultralow Power, Stereo Codec with Class H Headphone Am

10 DS851F2CS42L561.1 I/O Pin CharacteristicsInput and output levels and associated power supply voltage are shown in the table below. Logic levelsshou

DS851F2 11CS42L562. TYPICAL CONNECTION DIAGRAMS Note 1Note 22.2 µFNote 1Analog Input 1Analog Input 21 µFGND/Thermal PadVL0.1 µF+1.65 V to +3.63 VRESET

12 DS851F2CS42L562.2 µFNote 1**Note 22.2 µFNote 11 µFGND/Thermal PadVL0.1 µF+1.65 V to +3.63 VRESETRpLRCKMCLKSCLK+VHPFILTVDFILTLINEREFSDINSDOUTDigital

DS851F2 13CS42L56Note 1Note 22.2 µFNote 11 µFGND/Thermal PadVL0.1 µF+1.65 V to +3.63 VRESETRpLRCKMCLKSCLK2.2 µF+VHPFILTVDFILTLINEREFSDINSDOUTAIN1A1800

14 DS851F2CS42L563. CHARACTERISTIC AND SPECIFICATION TABLESRECOMMENDED OPERATING CONDITIONSGND = AGND = 0 V; all voltages with respect to ground. A

DS851F2 15CS42L56Dynamic Range A-weighted unweighted89869592--86839289--dBdBTotal Harmonic Distortion + Noise -1 dBFS-20 dBFS-60 dBFS----85-72-32-79-

16 DS851F2CS42L56Notes:5. See Figure 4.6. SDOUT Code with HPFx=1 and HPFRZx=0.7. See “Parameter Definitions” on page 91.8. The full scale input voltag

DS851F2 17CS42L56ADC DIGITAL FILTER CHARACTERISTICS Notes:11. Response is clock-dependent and will scale with Fs. Note that the response plots (Figu

18 DS851F2CS42L56HP OUTPUT CHARACTERISTICSTest conditions (unless otherwise specified): Connections to the CS42L56 are shown in the “Typical Connectio

DS851F2 19CS42L56LINE OUTPUT CHARACTERISTICSTest conditions (unless otherwise specified): Connections to the CS42L56 are shown in the “Typical Connect

2 DS851F2CS42L56SYSTEM FEATURES Audio (11.2896 MHz or 12.288 MHz) or USB (12 MHz) Master Clock Input Low-power Operation– Stereo Anlg. Passthrough:

20 DS851F2CS42L56Figure 6. HP Output Test ConfigurationTest LoadHPOUTxGND/AGNDCL0.1 µF33 HPREFRLMeasurement Device-+Symbolized compo-nent values are

DS851F2 21CS42L56ANALOG PASSTHROUGH CHARACTERISTICSTest Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the “Typical

22 DS851F2CS42L56SWITCHING SPECIFICATIONS - SERIAL PORTInputs: Logic 0 = GND = AGND, Logic 1 = VL, LRCK, SCLK, SDOUT CLOAD = 15 pF. Notes:20. After po

DS851F2 23CS42L56SWITCHING SPECIFICATIONS - I²C CONTROL PORTInputs: Logic 0 = GND = AGND, Logic 1 = VL (Note 22) .Notes:22. All specifications are val

24 DS851F2CS42L56SWITCHING CHARACTERISTICS - SPI CONTROL PORTInputs: Logic 0 = GND = AGND, Logic 1 = VL, SDA CL=30pF.Notes:24. Data must be held for s

DS851F2 25CS42L56ANALOG OUTPUT ATTENUATION CHARACTERISTICSTest Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the “T

26 DS851F2CS42L56DC CHARACTERISTICSTest Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the “Typical Connection Diagr

DS851F2 27CS42L56DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS31. See “I/O Pin Characteristics” on page 10 for serial and control port power

28 DS851F2CS42L56POWER CONSUMPTION - ALL SUPPLIES = 1.8 V Operation Test Condi-tions (unless otherwise specified): All zeros input, slave mode, sampl

DS851F2 29CS42L56POWER CONSUMPTION - ALL SUPPLIES = 2.5 V Notes:32. RESET pin and clock/data lines held LO, PDN=x.33. RESET pin held HI, PDN=1.34. Clo

DS851F2 3CS42L56TABLE OF CONTENTS1. PIN DESCRIPTIONS ...

30 DS851F2CS42L564. APPLICATIONS4.1 Overview4.1.1 Basic ArchitectureThe CS42L56 is a highly integrated, ultra-low power, 24-bit audio CODEC comprised

DS851F2 31CS42L564.2 Analog InputsReferenced Control Register LocationAnalog Front EndAIN1x_REFAIN2x_REFPREAMPx[1:0]PGAxMUX[1:0]PDN_ADCxPGAxVOL[5:0]PG

32 DS851F2CS42L564.2.1 Pseudo-differential InputsThe CS42L56 implements a pseudo-differential input stage. The AINxREF inputs are intended to be useda

DS851F2 33CS42L56If signals larger than what is shown in Table 1 are needed, an external resistor divider should be used asshown in Table 15. When usi

34 DS851F2CS42L564.2.3 Microphone Inputs Any of the line inputs can be configured as a microphone input by using the MICBIAS pin to power theexternal

DS851F2 35CS42L56whenever a threshold violation occurs. It then modifies the signal level by adjusting the gain settings inthe PGA and ADC digital vol

36 DS851F2CS42L564.2.5.1 Attack/Release Time Calculations:The time taken by the ALC to perform an attack or a release operation is a function of the P

DS851F2 37CS42L564.4 Analog Outputs Referenced Control Register LocationDSPPDN_DSPDEEMPHPMIXxMUTEPMIXxVOL[6:0]INV_PCMxPCMxSWAP[1:0]AMIXxMUTEAMIXxVOL[

38 DS851F2CS42L564.5 Class H AmplifierThe CS42L56 headphone and line output amplifiers use a Cirrus Logic patented Bi-Modal Class H technol-ogy. This

DS851F2 39CS42L564.5.1 Power Control OptionsThe method by which the CS42L56 decides which set of rail voltages is supplied to the amplifier outputstag

4 DS851F2CS42L564.11.2 Power-Down Sequence ... 504

40 DS851F2CS42L56ume setting should be factored in with the volume settings of other control blocks in the signal path.The Class H controller can be a

DS851F2 41CS42L56Effect of Volume Sum in HP or Line Paths Since the HP and the Line amplifiers also share the same sup-ply, the explanation above appl

42 DS851F2CS42L564.5.1.3 Adapt to Output Mode (setting 11)When the Adaptive Power bits are set to 11, the CS42L56 decides which of the two sets of rai

DS851F2 43CS42L564.5.3 EfficiencyAs discussed in previous sections, the amplifiers internal to the CS42L56 operate from one of two sets ofrail voltage

44 DS851F2CS42L56When the rail voltages are set to VCP, the amplifiers will operate in their least efficient mode. When therail voltages are held at ±

DS851F2 45CS42L564.7 LimiterWhen enabled, the limiter monitors the digital input signal before the DAC modulators, detects when levelsexceed the maxim

46 DS851F2CS42L564.8 Serial Port ClockingThe CODEC serial audio interface port operates either as a slave or master. It accepts externally generatedcl

DS851F2 47CS42L5624.0000(MKPREDIV=1b)(MCLKDIV2=1b)8.0000 3000 0.496 ~48 1110111.0294 2176 0.75 32 1101112.0000 2000 0.744 ~32 1100116.0000 1500 0.992

48 DS851F2CS42L56Referenced Control Register LocationSCK=MCK[1:0] ... MKPREDIV...MCLKDIV2...

DS851F2 49CS42L564.9 Digital Interface Format The serial port operates in standard I²S or Left-Justified digital interface formats with varying bit de

DS851F2 5CS42L566.11.2 HP/Line De-Emphasis ...

50 DS851F2CS42L564. Wait a minimum of 500 ns before writing to the control port.5. The default state of the master power down bit, PDN, is 1b. Load th

DS851F2 51CS42L56The CODEC will be fully powered down after this 100 µs delay. Prior to the removal of the master clock (MCLK), this delay of at least

52 DS851F2CS42L5613. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related

DS851F2 53CS42L564.13 Control Port OperationThe control port is used to access the registers allowing the CODEC to be configured for the desired oper-

54 DS851F2CS42L56register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows successivereads or writes of consecutive

DS851F2 55CS42L565. REGISTER QUICK REFERENCEDefault values are shown below the bit names. Unless otherwise specified, all “Reserved” bits must maintai

56 DS851F2CS42L561BhHPF CtlHPFB HPFRZB HPFA HPFRZA HPFB_CF1 HPFB_CF0 HPFA_CF1 HPFA_CF0p75 101000001ChMisc. ADC CtlADCB=A PGAB=A DIGSUM1 DIGSUM0 INV_AD

DS851F2 57CS42L566. REGISTER DESCRIPTION All registers are read/write except for the chip I.D. and revision register and the status register which are

58 DS851F2CS42L566.3.2 Power Down MIC BiasConfigures the power state of the microphone bias output. 6.3.3 Power Down ADC Charge PumpConfigures the pow

DS851F2 59CS42L566.4.2 Line Power Control Configures how the HPDETECT pin, 29, controls the power for the line amplifier.6.5 Clocking Control 1 (Addre

6 DS851F2CS42L566.27.1 PGA x Input Select ...

60 DS851F2CS42L566.5.5 MCLK DivideConfigures a divide of the MCLK after the MCLK pre-divide.6.5.6 MCLK DisableConfigures the MCLK signal prior to all

DS851F2 61CS42L566.6.2 Clock RatioConfigures the appropriate internal MCLK divide ratio for LRCK and SCLK.Notes:1. Register settings not shown in the

62 DS851F2CS42L566.8 Class H Control (Address 08h)6.8.1 Adaptive Power AdjustmentConfigures how the power to the headphone and line amplifiers adapts

DS851F2 63CS42L566.9.2 Analog Soft RampConfigures an incremental volume ramp from the current level to the new level at the specified rate. 6.9.3 Anal

64 DS851F2CS42L566.10 Status (Address 0Ah) (Read Only)Bits [6:0] in this register are “sticky”. 1b means the associated error condition has occurred a

DS851F2 65CS42L566.11 Playback Control (Address 0Bh)6.11.1 Power Down DSPConfigures the power state of the DSP Engine. 6.11.2 HP/Line De-EmphasisConfi

66 DS851F2CS42L566.12 DSP Mute Controls (Address 0Ch)6.12.1 ADC Mixer Channel x MuteConfigures a digital mute on the ADC mix in the DSP Engine. 6.12.

DS851F2 67CS42L566.14 PCMx Mixer Volume: PCMA (Address 0Fh) & PCMB (Address 10h)6.14.1 PCM Mixer Channel x VolumeSets the volume/gain of the PCM m

68 DS851F2CS42L566.15 Analog Input Advisory Volume (Address 11h)6.15.1 Analog Input Advisory Volume Defines the maximum analog input volume level used

DS851F2 69CS42L566.17 Master Volume Control:MSTA (Address 13h) & MSTB (Address 14h)6.17.1 Master Volume Control Sets the volume of the signal out

DS851F2 7CS42L56LIST OF FIGURESFigure 1.Typical Connection Diagram - Four Pseudo-Differential Analog Inputs ... 11F

70 DS851F2CS42L566.18.2 Beep On TimeSets the on duration of the beep signal. Notes:1. This setting must not change when BEEP is enabled.2. Beep on tim

DS851F2 71CS42L566.19.2 Beep Volume Sets the volume of the beep signal.6.20 Beep & Tone Configuration (Address 17h)6.20.1 Beep ConfigurationConfig

72 DS851F2CS42L566.20.3 Bass Corner Frequency Sets the corner frequency for the bass shelving filter.6.20.4 Tone Control Enable Configures the treble

DS851F2 73CS42L566.22 ADC & PCM Channel Mixer (Address 19h)6.22.1 PCM Mix Channel Swap Configures a mix/swap of the PCM Mix to the headphone/line

74 DS851F2CS42L566.23.3 ADC x Input SelectSelects the specified analog input signal into ADCx. Note: Pseudo-differential inputs are not available when

DS851F2 75CS42L566.25 Misc. ADC Control (Address 1Ch)6.25.1 ADC Channel B=AConfigures independent or ganged volume and mute control of the ADC. When e

76 DS851F2CS42L566.26 Gain & Bias Control (Address 1Dh)6.26.1 PGA x Preamplifier GainConfigures the gain of the PGA x preamp. 6.26.2 BoostxConfigu

DS851F2 77CS42L566.27.2 PGAx VolumeSets the volume/gain of the Programmable Gain Amplifier (PGA).Notes:1. Refer to Figure 37 and Figure 38 on page 89

78 DS851F2CS42L566.29 ALC Enable & Attack Rate (Address 22h)6.29.1 ALCxConfigures the automatic level controller (ALC). Notes:1. The ALC should o

DS851F2 79CS42L566.30.2 ALC Release RateSets the rate at which the ALC releases the analog and/or digital attenuation from levels below theMIN[2:0] th

8 DS851F2CS42L561. PIN DESCRIPTIONS Pin Name # Pin DescriptionSDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial a

80 DS851F2CS42L566.31.2 ALC Minimum ThresholdSets the minimum level at which to disengage the ALC’s attenuation or amplify the input signal at the re-

DS851F2 81CS42L566.32.3 Noise Gate Threshold and BoostTHRESH sets the threshold level of the noise gate. Input signals below the threshold level will

82 DS851F2CS42L566.34 Automute, Line & HP MUX (Address 27h)6.34.1 Auto MuteConfigures the state of the auto mute feature. When enabled, the analog

DS851F2 83CS42L566.35.2 Headphone Volume Control Sets the volume of the signal out of the headphone amplifier. Notes:1. The step size may deviate from

84 DS851F2CS42L56Notes:1. The step size may deviate from 1.0 dB. Refer to Figure 39 on page 89 and Figure 40 on page 89.2. See section “Analog Output

DS851F2 85CS42L566.38 Limiter Control, Release Rate (Address 2Dh)6.38.1 Peak Detect and LimiterConfigures the peak detect and limiter circuitry. Note

86 DS851F2CS42L566.39 Limiter Attack Rate (Address 2Eh)6.39.1 Limiter Attack Rate Sets the rate at which the limiter applies digital attenuation from

DS851F2 87CS42L567. PCB LAYOUT CONSIDERATIONS7.1 Power SupplyAs with any high-resolution converter, the CS42L56 requires careful attention to power su

88 DS851F2CS42L568. ANALOG VOLUME NON-LINEARITY (DNL & INL)PGA Volume SettingActual Output Volume, dB-8-6-4-2024681012-6-5-4-3-2-10123456789101112

DS851F2 89CS42L569. ADC & DAC DIGITAL FILTERS 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.91−100−90−80−70−60−50−40−30−20−100Frequency (normalized to Fs)M

DS851F2 9CS42L56-VHPFILT 11Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that provides the negative r

90 DS851F2CS42L5610.PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over th

DS851F2 91CS42L5611.PACKAGE DIMENSIONS(Unless otherwise specified, linear tolerance is ±0.05 mm, and angular tolerance is ±2 deg.)1. Controlling dimen

92 DS851F2CS42L5612.ORDERING INFORMATION13.REFERENCES1. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000. http://www.semico