Cirrus-logic AN368 Manuel d'utilisateur Page 80
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- Table des matières
- MARQUE LIVRES
- Application Note 1
- TRIAC Dimmable SSL Circuit 1
- Risk of Electric Shock 2
- TABLE OF CONTENTS 3
- 2 Introduction 6
- 2.1 Definition of Acronyms 7
- 2.2 Definition of Symbols 8
- 3 Design Process 9
- 3.1 Operating Parameters 9
- 3.2 Design Process 10
- 3.3 Design Procedure 11
- Overshoot 13
- Reflected 13
- [Eq. 10] 15
- [Eq. 7] 15
- [Eq. 8] 15
- [Eq. 9] 15
- [Eq. 34] 19
- [Eq. 35]N 19
- [Eq. 36] 19
- [Eq. 37] 20
- [Eq. 38] 20
- = 2 50ns 21
- 7+= 50 ns 21
- 22
- [Eq. 44] 23
- [Eq. 45] 23
- [Eq. 46] 24
- [Eq. 47] 24
- [Eq. 48] 24
- [Eq. 49] 24
- [Eq. 50] 25
- [Eq. 51] 26
- [Eq. 52] 27
- CS1630 /31 28
- CHx_OFF[2:0] 50ns= 29
- CH1CompGain 30
- CH2CompGain 30
- Synchronizer 33
- [Eq. 58] 34
- [Eq. 60] 36
- [Eq. 61] 36
- [Eq. 62] 36
- 3.4 Boost Stage Design 37
- Inductance 39
- 3.5 Completing the Design 40
- [Eq. 67] 41
- [Eq. 68] 41
- [Eq. 69] 41
- [Eq. 70] 43
- [Eq. 71] 44
- [Eq. 72] 45
- [Eq. 73] 45
- CS1630/31 46
- [Eq. 77] 47
- + [3:0] 4 = 47
- [Eq. 78] 47
- [Eq. 79] 48
- 1 + 5= 49
- 4 Design Example 52
- 4.1 Design Steps 52
- [Eq. 108] 56
- [Eq. 109] 56
- [Eq. 110] 56
- [Eq. 111] 56
- [Eq. 112] 56
- [Eq. 113] 57
- [Eq. 114] 57
- [Eq. 115] 57
- [Eq. 116] 57
- [Eq. 117] 57
- [Eq. 118] 58
- [Eq. 119] 58
- [Eq. 120] 58
- [Eq. 121] 58
- [Eq. 122] 58
- 4 1+1615+18– 8 + 59
- [Eq. 125] 60
- [Eq. 126] 60
- [Eq. 127] 60
- [Eq. 128] 60
- [Eq. 129] 60
- [Eq. 130] 61
- 4.2 Boost Stage Design 63
- [Eq. 133] 64
- [Eq. 134] 64
- [Eq. 135] 64
- [Eq. 136] 64
- [Eq. 137] 64
- 4.3 Completing the Design 65
- [Eq. 142] 68
- [Eq. 143] 68
- 5 Appendix 70
- 5.1 OTP Memory Map 70
- AN368REV2 71 71
- 72 AN368REV2 72
- AN368REV2 73 73
- 74 AN368REV2 74
- AN368REV2 75 75
- 5.2 Schematic 76
- 5.3 Dimensions 77
- 5.4 Bill of Materials 78
- 79 AN368REV2 79
- Figure 26. BOM (Page 2 of 2) 79
- Revision History 80
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