Cirrus-logic CS61880 Manuel d'utilisateur télécharger pdf (Page 55)

CS61880

DS450PP3 55

19.5 Receiver Analog Characteristics

(TA = -40° C to 85° C; TV+, RV+ = 3.3 V ±5%; GND = 0 V))

Notes: 10. Parameters guaranteed by design and characterization.

11. Using components on the CDB61880 evaluation board in Internal Match Impedance Mode.

12. Return loss = 20log10 ABS((Z1 + Z0) / (Z1 - Z0)) where Z1 - impedance of the transmitter or receiver,

and Z0 = cable impedance.

13. Assuming that jitter free clock is input to TCLK.

14. Jitter tolerance for 6 dB input signal levels. Jitter tolerance increases at lower frequencies. HDB3 coders

enabled.

15. In Data Recovery Mode.

16. Jitter Attenuator in the receive path.

Parameter Min. Typ Max Units

Allowable Cable Attenuation @ 1024 kHz - - - 12 dB

RTIP/RRING Input Impedance E1 120 Ω Load

(Internal Line matching mode) E1 75 Ω Load

Note 10

13k

Ω

RTIP/RRING Input Impedance E1 120 Ω Load

(External Line matching mode) E1 75 Ω Load

Note 10

13k

Ω

Receiver Dynamic Range 0.5 - - Vp

Signal to Noise margin (Per G.703, O151 @ 6 dB cable Atten). - -18 - dB

Receiver Squelch Level 150 mV

LOS Threshold - 200 - mV

LOS Hysteresis 50 mV

Data Decision Threshold

Note 10

41 50 59 % of

peak

Input Jitter Tolerance 1 Hz - 1.8 Hz

Notes 10, 14, 16 20 Hz - 2.4 kHz

18 kHz - 100 kHz

1.5

0.2

Input Return Loss 51 kHz - 102 kHz

102 kHz - 2048 kHz

Notes 10, 11, 12 2048 kHz - 3072 kHz

-18

-28

-30

-27

1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 69 70

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Cirrus-logic CS61880 Manuel d'utilisateur Page 55

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