Copyright  Cirrus Logic, Inc. 2013(All Rights Reserved)http://www.cirrus.com192-kHz Stereo DAC with Integrated PLLFeatures Advanced multibit delta-s

10 DS691F2CS4350Figures 3 through 5 show typical THD+N performance for CS4350 devices that exhibit the maximum full scale out-put voltages as specifie

DS691F2 11CS43502.5 Combined Interpolation and On-Chip Analog Filter ResponseThe filter characteristics have been normalized to the sample rate (Fs) a

12 DS691F2CS43502.6 Switching Specifications - Serial Audio InterfaceInputs: Logic 0 = GND; Logic 1 = VLS; CL=20pF. Note: 10. RMCK output frequency de

DS691F2 13CS43502.7 Switching Characteristics - Control Port - I²C FormatInputs: Logic 0 = GND; Logic 1 = VLC; CL=20pF.Note: 11. Data must be held for

14 DS691F2CS43502.8 Switching Characteristics - Control Port - SPI Format Inputs: Logic 0 = GND; Logic 1 = VLC; CL=20pF. Notes: 12. tspi only needed b

DS691F2 15CS43502.9 Digital Characteristics2.10 Power and Thermal CharacteristicsNotes: 16. Current consumption increases with increasing Fs within th

16 DS691F2CS43503 TYPICAL CONNECTION DIAGRAM DigitalAudioSourceVLSGNDCS4350RMCKAOUTA+0.1 µF+10 µFµ C/ModeConfigurationSDINDIF1(SCL/CCLK)DIF0(SDA/CDI

DS691F2 17CS43504 APPLICATIONS4.1 Sample Rate Range and Oversampling Mode DetectThe device operates in one of three oversampling modes based on the in

18 DS691F2CS43504.3 Digital Interface FormatThe device will accept audio samples in 1 of 8 digital interface formats, as shown in Table 12 on page 23f

DS691F2 19CS43504.3.1 Time-Division Multiplex (TDM) ModeFour TDM interface modes are available that allow the CS4350 to input stereo PCM data in one o

2 DS691F2CS4350DescriptionThe CS4350 is a complete stereo digital-to-analog system including PLL-based master clock derivation, digital in-terpolation

20 DS691F2CS43504.4 De-EmphasisThe device includes on-chip digital de-emphasis. Figure 16 shows the de-emphasis curve for Fs equal to44.1 kHz. The fre

DS691F2 21CS43504.6.2 Control Port Mode1. Hold RST low until the power supply is stable and the left/right clock is fixed to the appropriate frequency

22 DS691F2CS43504.8 Analog Output and FilteringThe Cirrus Application Note titled Design Notes for a 2-Pole Filter with Differential Input, available

DS691F2 23CS43505 STAND-ALONE OPERATION5.1 Serial Port Format SelectionThe desired serial audio format is selected with the DIF2, DIF1 and DIF0 pins.

24 DS691F2CS4350enable the user to alter the chip address (10010[AD1][AD0][R/W]) and should be tied to VLC or GND asrequired before powering up the de

DS691F2 25CS4350 6.3 SPI ModeIn SPI Mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK(see Figure 2

26 DS691F2CS43506.4 Memory Address Pointer (MAP) 6.4.1 INCR (Auto Map Increment Enable)Default = ‘0’0 - Disabled1 - Enabled6.4.2 MAP (Memory Address P

DS691F2 27CS43507 REGISTER QUICK REFERENCEAddr Function 7 6 5 4 3 2 1 01h Device and RevID DeviceID4 DeviceID3 DeviceID2 DeviceID1 DeviceID0 RevID2 Re

28 DS691F2CS43508 REGISTER DESCRIPTIONNote: All register access is Read/Write unless specified otherwise8.1 Device and Revision ID - Register 01h Func

DS691F2 29CS43508.2.2 De-Emphasis Control (DEM[1:0]) Bits 3-2 Default = 000 - No De-emphasis01 - 44.1 kHz De-emphasis10 - 48 kHz De-emphasis11 - 32 kH

DS691F2 3CS4350TABLE OF CONTENTS1 PIN DESCRIPTION...

30 DS691F2CS43508.3.3 Invert Signal Polarity (INVERT_B) Bit 5Function:When set to 1, this bit inverts the signal polarity of channel B.When set to 0 (

DS691F2 31CS43508.4 Mute Control - Register 04h 8.4.1 Auto-Mute (AMUTE) Bit 7Function:When set to 1 (default), the Digital-to-Analog converter output

32 DS691F2CS43508.5 Channel A & B Volume Control - Register 05h & 06h Digital Volume Control (VOL[7:0]) Bits 7-0Default = 00h (0 dB) Function:

DS691F2 33CS4350Soft Ramp and Zero CrossSoft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut-ing, w

34 DS691F2CS43508.7.2 Freeze Controls (FREEZE) Bit 5Function:When set to 1, this function allows modifications to be made to the registers without the

DS691F2 35CS43509 FILTER PLOTS 0.4 0.5 0.6 0.7 0.8 0.91120100806040200Frequency(normalized to Fs)Amplitude (dB)Figure 23. Stopband Rejection (fast

36 DS691F2CS435010 PARAMETER DEFINITIONSTotal Harmonic Distortion + Noise (THD+N)The ratio of the rms value of the signal to the rms sum of all other

DS691F2 37CS435011 PACKAGE DIMENSIONS1. D” and “E1” are reference datums and do not include mold flash or protrusions, but do include moldmismatch and

38 DS691F2CS435013 ORDERING INFORMATION14 REVISION HISTORY Product Description PackagePb-FreeGrade Temp Range ContainerOrder#CS4350192 kHz Stereo DAC

4 DS691F2CS43508.2.2 De-Emphasis Control (DEM[1:0]) Bits 3-2 ... 298.2.3 Funct

DS691F2 5CS4350LIST OF FIGURESFigure 1. Equivalent Output Load ...

6 DS691F2CS43501 PIN DESCRIPTIONPin Name # Pin DescriptionVLC5Control Interface Power (Input) - Positive power for the hardware/software control inter

DS691F2 7CS43502 CHARACTERISTICS AND SPECIFICATIONS 2.1 Recommended Operating ConditionsGND = 0 V; all voltages with respect to ground.2.2 Absolute Ma

8 DS691F2CS43502.3 DAC Analog Characteristics - Commercial (-CZZ)Test conditions (unless otherwise specified): VLS = VLC = 3.3 V; TA = 25° C; Input te

DS691F2 9CS43502.4 DAC Analog Characteristics - Automotive (-DZZ)Test conditions (unless otherwise specified): VLS = 1.35 V to 5.25 V, VLC = 3.14 V to