Cirrus-logic CS42L52 Manuel d'utilisateur télécharger pdf (Page 73)

DS680F2 73

CS42L52

3/1/13

6.39.2 SPKR/HP Pin Status (Read Only)

Indicates the status of the SPKR/HP pin.

6.40 Charge Pump Frequency (Address 34h)

6.40.1 Charge Pump Frequency

Sets the charge pump frequency on FLYN and FLYP.

Note: The headphone output THD+N performance may be affected.

SPKR/HP Pin State

0 Pulled Low

1 Pulled High

76543210

CHGFREQ3 CHGFREQ2 CHGFREQ1 CHGFREQ0 Reserved Reserved Reserved Reserved

CHGFREQ[3:0] N

0000 0

...

0101 5

...

1111 15

Formula: Frequency = (64xFs)/(N+2)

1 2 ... 68 69 70 71 72 73 74 75 76 77 78 ... 81 82

Stereo CODEC 1
Stereo Headphone Amplifier 1
System Features 2
™ Control Port Operation 2
Applications 2
General Description 2
TABLE OF CONTENTS 3
LIST OF TABLES 7
LIST OF FIGURES 7
1. PIN DESCRIPTIONS 8
DS680F2 9 9
1.1 I/O Pin Characteristics 10
2. TYPICAL CONNECTION DIAGRAM 11
ABSOLUTE MAXIMUM RATINGS 12
DS680F2 13 13
VA = 2.5V VA = 1.8V 13
14 DS680F2 14
PWM OUTPUT CHARACTERISTICS 17
0.022 F 18
Repeated 21
(Note 18) 22
(Note 23) 23
4. APPLICATIONS 24
4.2 Analog Inputs 25
4.2.1 MIC Inputs 26
4.2.3 Noise Gate 27
4.3 Analog Outputs 28
4.3.1 Beep Generator 29
4.3.2 Limiter 30
RRATE[5:0]ARATE[5:0] 31
4.5 PWM Outputs 32
4.5.2 VP Battery Compensation 33
4.6 Serial Port Clocking 33
34 DS680F2 34
4.7.1 DSP Mode 35
4.8 Initialization 36
4.12 Control Port Operation 38
4.12.1 I²C Control 38
4.12.2.1 Map Increment (INCR) 39
5. REGISTER QUICK REFERENCE 40
DS680F2 41 41
6. REGISTER DESCRIPTION 42
6.4.1 Headphone Power Control 44
6.4.2 Speaker Power Control 44
6.5.1 Auto-Detect 44
6.5.2 Speed Mode 45
6.5.3 32kHz Sample Rate Group 45
6.5.4 27 MHz Video Clock 45
(Examples) 49
50 DS680F2 50
INV_ADCx ADC Signal Polarity 51
ADCxMUTE ADC Mute 51
INV_PCMx PCM Signal Polarity 52
MSTxMUTE Master Mute 52
PASSxMUTE Passthrough Mute 52
FREEZE Control Port Status 52
6.13.4 HP/Speaker De-emphasis 53
6.13.5 Digital Soft Ramp 53
6.13.6 Digital Zero Cross 53
DS680F2 55 55
6.16.3 PGAx Volume 56
6.17.1 Passthrough x Volume 57
6.18.1 ADCx Volume 57
58 DS680F2 58
6.21.1 Beep Frequency 59
6.21.2 Beep On Time 60
6.22.1 Beep Off Time 60
6.22.2 Beep Volume 61
6.23.1 Beep Configuration 61
6.23.2 Beep Mix Disable 61
62 DS680F2 62
6.24.2 Bass Gain 63
6.25.1 Master Volume Control 63
6.28.1 PCM Mix Channel Swap 64
6.28.2 ADC Mix Channel Swap 64
6.33.1 ALC Release Rate 68
6.34.1 ALC Maximum Threshold 68
6.37.3 VP Reference 72
6.40.1 Charge Pump Frequency 73
7. ANALOG PERFORMANCE PLOTS 74
8.1 Auto Detect Enabled 76
8.2 Auto Detect Disabled 76
9. PCB LAYOUT CONSIDERATIONS 77
78 DS680F2 78
11.PARAMETER DEFINITIONS 79
12.PACKAGE DIMENSIONS 80
THERMAL CHARACTERISTICS 80
13.ORDERING INFORMATION 81
14.REFERENCES 81
15.REVISION HISTORY 81
82 DS680F2 82

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Cirrus-logic CS42L52 Manuel d'utilisateur Page 73

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