Cirrus-logic CDB61880 Manuel d'utilisateur Page 1

Preliminary Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without not

CDB6188010 DS450DB14. HOST SOFTWARE INTERFACEThe software provided with the CDB61880 evalu-ation board is used to control and monitor theCS61880 devi

CDB61880DS450DB1 114.3.1 Clear All Button DescriptionThe CLR All Button shown Figure 14 is used to setall the bits in the corresponding register to 0

CDB6188012 DS450DB15. CS61880 CONFIGURATION SCREENS 5.1 Choose Parallel Port SettingsThe opening screen shown before in Figure 11 andnow in Figure 1

CDB61880DS450DB1 135.3 Loopback /Bits Clock ScreenThe Loopback /Bits Clock Register tabbed screenshown in Figure 20 allows access to the followingreg

CDB6188014 DS450DB15.4 LOS/AIS/DFM/JA Register ScreenThe LOS/AIS/DFM/JA Register tabbed screenshown in Figure 21 allows access to the followingregist

CDB61880DS450DB1 155.5 Transmitter Register ScreenThe Transmitter Register screen shown inFigure 22 consists of the following registers: - Automatic

CDB6188016 DS450DB15.6 AWG Register ScreenThe AWG Register screen shown in Figure 23 al-lows access to the following AWG registers: - AWG Broadcast-

CDB61880DS450DB1 175.7 Global Control Register ScreenFigure 24 shows the Global Control Register(GCR) screen, The GCR register screen consists ofthe

CDB6188018 DS450DB16. BOARD CONFIGURATIONS6.1 E1 75 ΩΩΩΩ Mode SetupTable 4 shows the position of the different switchesand jumpers used to set up th

CDB61880DS450DB1 196.2 E1 120 ΩΩΩΩ Mode SetupTable 5 shows the position of the different switchesand jumpers used to set up the CDB61880 evalua-tion

CDB618802 DS450DB1TABLE OF CONTENTS1. CDB61880 EVALUATION BOARD LAYOUT ... 42

CDB6188020 DS450DB17. EVALUATION HINTS- Pin #1 of the socket is indicated by an arrow with U1 below it.- A short in the desired position must be plac

• Notes •

CDB61880DS450DB1 35.1 Choose Parallel Port Settings ... 125.2 A

CDB618804 DS450DB11. CDB61880 EVALUATION BOARD LAYOUTFigure 1. CDB61880 Board Layout

CDB61880DS450DB1 52. BOARD COMPONENT DESCRIPTIONS2.1 Power Connections Power for the CDB61880 evaluation board is sup-plied by an external +3.3 V DC

CDB618806 DS450DB12.3 Operating Mode SelectionThe operating mode for the CS61880 can be select-ed by setting switch S15 to one of the positionsshown

CDB61880DS450DB1 7mitters in a high impedance state. Removing theshorting block, enables the transmitters. SeeFigure 5.2.6 Clock Edge SelectionIn clo

CDB618808 DS450DB12.9 Line Length/Impedance SelectionIn Hardware mode, switch S11 (CBLSEL) is usedto set the internal or external line impedance for

CDB61880DS450DB1 92.13 Digital Signal ConnectionsThere are eight fourteen pin bed stake headers (la-beled J4 through J11) that provide access to thed