Cirrus-logic CDB48500-USB Manuel d'utilisateur

http://www.cirrus.comCDB48500High-performance, 32-Bit Audio Decoder DSP FamilyCopyright  Cirrus Logic, Inc. 2014(All Rights Reserved)CDB48500-USB USB

1 Chapter 2Board Setup and Installing the Evaluation Kit Software 2.1 IntroductionIt is important to install the Evaluation Software BEFORE connectin

2 8. The Opal Kelly Licensing Agreement window will appear next. Click “I Agree” to agree to the terms and continue.9. The next window asks the user

3 B. Connect the other end of the optical cable to the optical output on the back of a DVD player or other digital audio source.5. Setup Audio Output

4 Figure 2-5. Found New Hardware Wizard Finish Window6. It is possible that during the installation, Windows might issue a warning that the drivers

5 2.1.4 Running a Stereo PCM Application on CDB48500-USBTo run a stereo PCM application, follow these steps:1. Launch DSP composer (Start Program 

1 Chapter 3CDB48500 System DescriptionA detailed block diagram of the CDB48500 Customer Development Board is shown in Figure 3-1. The sections that f

2 3.1 CDB48500 System Block Descriptions 3.1.1 Audio Inputs 3.1.1.1 Analog Line-level Inputs• Connector Type: RCA Female• Absolute Maximum Signal Le

3 3.1.2.3 Optical Digital Output (PCM)• Connector Type: Fiber Optic TX for Digital Audio, JIS F05 (JIS C5974-1993 F05)• Reference Designator: J24, o

4 3.1.6 Audio Input Source Multiplexer Selection HeadersThe CDB48500-USB includes jumpers to change DSP DAI inputs.• Source 0: CDB USB MASTER Board,

5 3.1.8 CS8416 S/PDIF RXThe CS8416 (U3) is a 192 kHz S/PDIF receiver with an integrated input multiplexer. The two S/PDIF input jacks (RXP-RXN) are

ii CDB48500 USB Evaluation Kit Guide CDB48500 Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Rep

6 3.1.11.1 Clock and Data Flow for up to 8 Channel ADC inputs Figure 3-2. Simplified Clock and Data Flow for up to 8 Channel ADC Inputs The ADC clo

7 3.1.11.2 Clock and Data Flow for S/PDIF Input Figure 3-3. Simplified Clock and Data Flow for S/PDIF InputFigure 3-3 illustrates the S/PDIF clocki

8 3.1.11.3 Clock and Data Flow for CDB USB Master Card Source Figure 3-4. CDB USB Master Card Clocking and Data FlowFigure 3-4 illustrates the clo

1 Chapter 4Configuring the CDB48500 4.1 IntroductionThe DSP Composer™ software is a graphical user interface (GUI) that is used to program the CS485X

2 4.2.1 System BlockThe CDB48500 board is populated with a CS48560. However it is possible to evaluate the CS48520, CS48540, CS48560, CS485AU2B, and

3 Figure 4-3. Audio In via S/PDIF In 4.2.2.2 Audio In via 8-channel ADCTo deliver data to the DSP via 8ch ADC, drag the Audio In block to the work s

4 4.2.2.4 DAI Input of CS485xxEach of the Audio In Elements listed above are connected to a DAI element. This represent the DAI port of the DSP. As

5 . Figure 4-6. CDB48500 Digital Audio Output PropertiesThis dialog allows the user to set the following parameters for the CS485XX Audio Output:• LR

6 . Figure 4-7. Codec DAC PropertiesThis Audio Out dialog allows the user to set the following parameters for the CS42448 DACs:• Audio Data Format -

7 . Figure 4-8. CDB48500 Comm Mode

CDB48500 USB Evaluation Kit Guide iiiCDB48500 Contents Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 4.2.5 Headphone OutputThe CDB48500 is designed with one Stereo Headphone output. The content of the Headphone output is controlled by the Remap ta

1 Appendix ASchematics A.1 IntroductionUpdates to the schematics for the CDB48500 Development Board can be can be obtained from your local Cirrus Lo

2 clock domain (MUXED_SCLK, MUXED_LRCLK). On the audio outputs, the CS485XX is slave-only for the MUXED_MCLK master audio clock, and master-only for

3 The CS42448_RST signal is a dedicated reset signal driven by a general-purpose output of the CS8416.The CS42448 is a slave to the MUXED_MCLK signal

4 A.1.1.1.8 Codec 1 and Codec 2 Input Filters (See Figure 1-8)Each input of the CS42448 has its own input filter that consists of a voltage divider,

DS784DB2 Copyright 2014 Cirrus Logic A-5 Figure A-1. CS48500 System Block Diagram

DS784DB2 Copyright 2014 Cirrus Logic A-6 Figure A-2. DSP Input Data Multiplexing Schematic

DS784DB2 Copyright 2014 Cirrus Logic A-7 Figure A-3. DSP Schematic

DS784DB2 Copyright 2014 Cirrus Logic A-8 Figure A-4. Serial Flash Memory Schematic

DS784DB2 Copyright 2014 Cirrus Logic A-9 Figure A-5. SPDIF Receiver Schematic

iv CDB48500 USB Evaluation Kit Guide CDB48500 Chapter 4. Configuring the CDB48500... 4-1

DS784DB2 Copyright 2014 Cirrus Logic A-10 Figure A-6. Codec #1(CS42448) Schematic

DS784DB2 Copyright 2014 Cirrus Logic A-11 Figure A-7. Codec #2 (CS42448) Schematic

DS784DB2 Copyright 2014 Cirrus Logic A-12 Figure A-8. Codec 1 and Codec 2 Input Filters Schematic

DS784DB2 Copyright 2014 Cirrus Logic A-13 Figure A-9. Output Filters & Headphone Output Schematic

DS784DB2 Copyright 2014 Cirrus Logic A-14 Figure A-10. Mic Preamp Schematic

DS784DB2 Copyright 2014 Cirrus Logic A-15 Figure A-11. Control Connector and Power Schematic§§

1 Appendix BTroubleshooting Guide B.1 IntoductionThis chapter describes many common problems users may have with the CDB48500-USB, possible causes,

2 Revision HistoryRevision Date ChangesDB1 September, 2006 Initial releaseDB2 February, 2014Added Windows 7® to list of PC requirements in Section 1.

CDB48500 USB Evaluation Kit Guide vCDB48500 Figures Figure 1-1. CDB48500-USB System Block Diagram ...

1 Chapter 1Introduction to the CRD48500-USB Evaluation Kit 1.1 CDB48500-USB Kit Contents and Requirements 1.1.1 CDB48500-USB KitEach CDB48500-USB kit

2 between the PC, CS485XX, and the CDB USB MASTER Figure 1-1. CDB48500-USB System Block DiagramThis document will concentrate on the features and bas

DS784DB2 Copyright 2014 Cirrus Logic 1-3 Figure 1-2. CDB48500-USB Top ViewLegend:A.CS485XX DSP, U6 B.CS42448 Audio CODEC, U4 C.CS42448 Audio CODEC, U

4 1.2.2 Related Documentation The documents described in this section are updated periodically and may be more up-to-date than the information in th