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Copyright  Cirrus Logic, Inc. 2012(All Rights Reserved)Cirrus Logic, Inc.http://www.cirrus.comApplication NoteDesign Guide for a CS1630/31 2-ChannelT

AN36810 AN368REV23.2 Design ProcessThe design process requires a specification covering the required operating range, color temperature, dimmer compat

AN368AN368REV2 113.3 Design ProcedureStep 1) Select Input VoltageThe CS1630 is optimized for 120VAC line voltage applications and designs targeting 1

AN36812 AN368REV2Step 3) Determine Second-stage Parameters for a Flyback TopologyFigure 3 illustrates the steps for designing the second stage.Steps

AN368AN368REV2 13a. Set the Value for Boost Output VoltageThe value of the boost output voltage VBST must be greater than the maximum input AC line vo

AN36814 AN368REV2For optimum efficiency, the increase in transformer losses (created by an uneven duty cycle) must balance the reduction of the losses

AN368AN368REV2 15The minimum switching frequency Fsw(min) for the second stage is configured to provide good power regulation. The minimum switching f

AN36816 AN368REV2Calculate Mode 1 duty ratio DMODE1 and Mode 2 duty ratio DMODE2 using Equations 11 and 12, respectively:Assuming the resonant times T

AN368AN368REV2 17Calculate the MOSFET ‘OFF’ time T2CH1 in Mode 1 using Equation 22:Calculate the MOSFET ‘OFF’ time T2CH2 in Mode 2 using Equation 23:f

AN36818 AN368REV2The RMS current in the secondary winding ISEC(RMS) is calculated using Equation 30:i. Calculate RSense (R21)A scaling factor is used

AN368AN368REV2 19The FBAUX pin current must be limited to less than 1mA. Resistor R22 plus resistor R23 should be chosen such that current VAUX/(R22 +

AN3682 AN368REV2Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one ne

AN36820 AN368REV2m. Recalculate RSense The flyback primary current is controlled by comparing the voltage across RSense at pin FBSENSE to an internal

AN368AN368REV2 21c. Trailing-edge BlankingConfigurable blanking time on the zero-current detection (ZCD) comparator provides protection to suppress fa

AN36822 AN368REV2g. Automated Resonant Period MeasurementsTo ensure accuracy of the T2 duration measurements within the CS1630 controller, the resonan

AN368AN368REV2 23h. Switching Frequency Across Dim RangeFrom the equations below and setting the OTP registers as follows, the switching frequency acr

AN36824 AN368REV2Frequency in Region CIn Region C, the switching frequency is kept constant, and the peak current IPK(FB) starts to reduce. Period TTC

AN368AN368REV2 25The linearity of the second-stage current regulation is determined by the error between the expected currents at any given dim level

AN36826 AN368REV2c. Tune IPK(FB) Compensations for Optimum Linear PerformanceTo achieve high accuracy for the output current, it is essential to obtai

AN368AN368REV2 27d. Set T2 Offset Delays to Get Optimum Linear PerformanceA delay is present between the time the primary current reaches zero and the

AN36828 AN368REV2Time T2CHx offset delays cause errors when calculating average current regulation using Equations 27 and 28. Averaged output current

AN368AN368REV2 29Times T2CH1OFF and T2CH2OFF are offset delays that assist in achieving the desired linear performance on the output currents across d

AN368AN368REV2 3TABLE OF CONTENTS1 OVERVIEW OF THE CS1630 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AN36830 AN368REV2e. T2 Commutation Time Delay CompensationThe presence of circuit parasitic components, such as leakage inductance, causes a delay bet

AN368AN368REV2 31f. Procedure for Measuring the Second-stage Output Current RegulationThis step describes the procedure for measuring the second-stage

AN36832 AN368REV23. Disable the color system and boost stage by forcing gains GAINDR and GAINDTR to a value of 1 and theconverter to a flyback-only st

AN368AN368REV2 33b. Flyback Mode Operation Using a Dual LED String Synchronizer CircuitThe dual-LED string load is implemented in a series output conf

AN36834 AN368REV2Component U2 is a positive edge D-type flip-flop and is used as a frequency divider. The output terminal Q is connected to input D. T

AN368AN368REV2 35c. Synchronizer Circuit RC Filter DesignThe Synchronizer Circuit has an RC filter in the feedback path from Q to D. This circuit shou

AN36836 AN368REV2One of the LED strings is composed of red or amber LEDs, and the other string is composed of cool-white or blue-white LEDs. While the

AN368AN368REV2 373.4 Boost Stage DesignThe design process for the boost stage is outlined below:1. Determine IPK(BST) and a tentative IPK(BST) OTP set

AN36838 AN368REV2The AC line current does not follow the inductor peak current envelope because the circuit operates in CRM and DCM. The switching fre

AN368AN368REV2 39The frequency range should be as high as possible without exceeding 75kHz. This strategy keeps the fundamental and second harmonic be

AN3684 AN368REV2Step 9) Boost Inductor Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AN36840 AN368REV2Step 10) Determine Boost Output CapacitorThe boost stage output capacitor is also the flyback stage input capacitor. Determine the si

AN368AN368REV2 41Step 14) Boost Zero-current DetectionThe CS1630 uses zero-current detection (ZCD) to minimize switching losses. The ZCD algorithm is

AN36842 AN368REV2b. Overcurrent ProtectionOvercurrent protection (OCP) is designed to detect when the current-sensing resistor RSense is open circuite

AN368AN368REV2 434. Configure the threshold for the OLP event accumulator used to declare an OLP fault. BitsOLP_CNT[2:0] in register Config49 at Addre

AN36844 AN368REV2e. Short Circuit ProtectionShort circuit protection (SCP) is designed to detect when either of the channels is short circuited and pr

AN368AN368REV2 45h. Clamp Overpower ProtectionClamp overpower protection (COP) is designed to detect when the boost voltage exceeds a specified thresh

AN36846 AN368REV2j. External Overtemperature ProtectionThe external overtemperature protection (eOTP) pin is used to implement overtemperature protect

AN368AN368REV2 47When exiting reset, the chip enters startup and the ADC quickly (<5ms) tracks the external temperature to check if it is below Tem

AN36848 AN368REV25. The first filtered output is compared against a programmable code value that corresponds to the desiredshutoff temperature set poi

AN368AN368REV2 499. Configure the second-stage dim level adjustment using the external temperature. The external NTCconnected to the eOTP pin is used

AN368AN368REV2 5c. Tune IPK(FB) Compensations for Optimum Linear Performance . . . . . . . . . . . . . . . . . . . . . . 60d. Set T2 Offset Delays

AN36850 AN368REV2The EMI filter and the reactances associated with the dimmer constitute a complex reactive network that has minimal damping. This rea

AN368AN368REV2 51Step 18) LayoutBasics for any power layout are as follows:• Keep power traces as short as possible.• Keep the controller away from po

AN36852 AN368REV24 Design ExampleThe Cirrus Logic CRD1630-9W reference design is used for the design example. The required operating parameters for th

AN368AN368REV2 53It is recommended to choose VReflected to equal 37% of VZener. Voltage VReflected is set to 116.6V, leaving 183V overshoot to dissipa

AN36854 AN368REV2e. Determine the Flyback Nominal Timing T1 and T2Calculate Mode 1 duty ratio DMODE1, and Mode 2 duty ratio DMODE2, using Equations 11

AN368AN368REV2 55Calculate the MOSFET ‘ON’ time T1CH1 in Mode 1 using Equation 20:Calculate the MOSFET ‘ON’ time T1CH2 in Mode 2 using Equation 21:Cal

AN36856 AN368REV2h. Determine the RMS Current in the WindingThe RMS current in the primary winding, IPRI(RMS), is calculated using Equation 29:The RMS

AN368AN368REV2 57The FBAUX pin current must be limited to less than 1mA. Resistor R22 plus R23 should be chosen such that current VAUX/(R22 + R23) sho

AN36858 AN368REV2m. Recalculate RSenseOnce the current sense resistor RSense value is determined, the target output current CH1CUR for channel 1 is ca

AN368AN368REV2 59e. Minimum Measurable Peak CurrentThe minimum peak current level bits IPEAK[2:0] in register Config3 at Address 35 are set to ‘100’ a

AN3686 AN368REV22 IntroductionThis application note provides a guide to designing a solid-state lighting (SSL) LED lamp circuit using Cirrus Logic&apo

AN36860 AN368REV22. Disabling automatic TRES probing and fixing the TRES probe count will resolve theproblem. This has the disadvantage that if the re

AN368AN368REV2 61f. Procedure for Measuring the Second-stage Output Current RegulationMeasurement of second-stage output current regulation is require

AN36862 AN368REV2Design Tip - Frequent re-syncing events on the second stageSymptoms: The current in either channel keeps changing by 1mA to 3mA in e

AN368AN368REV2 63The minimum dim setting for the second stage is configured using the S2DIM register at Address 37. The enforced minimum dim percentag

AN36864 AN368REV2The PEAK_CUR register at Address 51 is used to store IPK(code). Maximum power output is proportional to IPK(code). Using Equation 133

AN368AN368REV2 654.3 Completing the DesignStep 12) Choose Power ComponentsThe maximum drain current through transistor Q4 is limited to 297.5mA. The s

AN36866 AN368REV2Design Tip - Sense resistor is open circuited or unusually largeCheck: Determine if the power supply is operating in either auto-res

AN368AN368REV2 67Design Tip - Prevent output current from exceeding VOVP(th) if one channel is open circuitedCheck: Determine if the power supply is o

AN36868 AN368REV2j. External Overtemperature ProtectionThe external negative temperature coefficient (NTC) thermistor reference is a Murata NCP18WF104

AN368AN368REV2 69Step 17) Designing the EMI FilterLimitations are imposed on the values of the inductance, capacitance, and resistance assigned to the

AN368AN368REV2 72.1 Definition of AcronymsAcronym DescriptionPFC Power Factor CorrectionZCD Zero-current DetectionBOP Boost Overvoltage ProtectionCOP

AN36870 AN368REV25 Appendix5.1 OTP Memory MapAddName765432100Config0- - - - - - MODE LOCKOUT000000001LOCK3231230229228227226225224000000002LOCK2223222

AN368AN368REV2 7119 P12_MSB-(23) 2221202-12-22-32-40000000020 P12_LSB2-52-62-72-82-92-102-112-121101101021 P11_MSB-(23) 2221202-12-22-32-41111010022 P

AN36872 AN368REV239 Config7PROBE PRCNT[3:0] - - -1111101040 Config8RSHIFT[3:0] CH1_ZCD[2:0]CH1CURMSB1100110041 CH1CUR27262524232221201111111042 Config

AN368AN368REV2 7366 Reserved0101000067 Reserved1001010068 Reserved0001000169 Reserved1000111070 Config38- - - - - - - CRC1000101171 Reserved0110110072

AN36874 AN368REV291 Config59eOTP[4:0] HI_SAT[2:0]1111010092 Config60- PLC - CS_DELAY[2:0] - -1011111193 Config61DITNODIM DITLEVEL[1:0] DITCHAN - - - -

AN368AN368REV2 75123 CH2_CAL3B- - CH2_CAL3B[5:0]00000000124 CRC_MTAG3B272625242322212000000000125 CH1_CAL3CSET_3C - CH1_CAL3C[5:0]00000000126 CH2_CAL3

AN36876 AN368REV25.2 SchematicFigure 23. Schematic

AN368AN368REV2 775.3 DimensionsR+R-W+W-TX1L3C1R9R11C4L2FH1C11Q2Q5C13C23L1C8C15NLC6Q1NTC+J12J13J7J8J9J14C201.025 "2.050 "0.625 "1.310 &q

AN36878 AN368REV25.4 Bill of MaterialsFigure 25. BOM (Page 1 of 2)Item Designator Value Manufacturer Part Number Package Per Qty Assembly Notes1BR1HD

AN36879 AN368REV2Item Designator Value Manufacturer Part Number Package Per Qty Assembly Notes42-43L1, L2 COILCRAFT 3.3mH Drum Inductor Coilcraft RFB0

AN3688 AN368REV22.2 Definition of SymbolsSymbol DescriptionFswSecond-stage switching frequencyFsw1 & Fsw2Switching frequency for channel 1 and cha

AN36880 AN368REV2Revision HistoryRevision Date ChangesREV1 SEP 2012 Initial Release.REV2 DEC 2012 Context clarifications and typographical errors corr

AN368AN368REV2 93 Design ProcessThe design process for a two-stage power converter system can be partitioned into seven circuit blocks (see Figure 1).