Cirrus-logic CS5526 Manuel d'utilisateur

Copyright © Cirrus Logic, Inc. 2005(All Rights Reserved)http://www.cirrus.comCS5525 CS552616-bit/20-bit, Multi-range ADC with 4-bit LatchFeaturesz Del

CS5525 CS552610 DS202F5System InitializationWhen power to the CS5525/26 is applied, they areheld in a reset condition until their 32.768 kHz os-cillat

CS5525 CS5526DS202F5 11Reading/Writing On-Chip RegistersThe CS5525/26’s offset, gain, and configurationregisters are read/writable while the conversio

CS5525 CS552612 DS202F5Configuration Register* R indicates the bit value after the part is resetD23(MSB) D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12A3

CS5525 CS5526DS202F5 13 Command Time8 SCLKsData Time 24 SCLKs(or 72 SC LKs for Set-up R egisters)Write CycleCSSCLKSDIMSBLSBCommand Time8 SCLKsCSSCLKS

CS5525 CS552614 DS202F5Analog InputFigure 7 illustrates a block diagram of the analog in-put signal path inside the CS5525/26. The front endconsists o

CS5525 CS5526DS202F5 15differential output voltage from the amplifier ex-ceeds 2.8 V, the amplifier may saturate, which willcause a measurement error.

CS5525 CS552616 DS202F5Charge Pump DriveThe CPD (Charge Pump Drive) pin of the convert-ers can be used with external components (shownin Figure 1) to

CS5525 CS5526DS202F5 17The offset and gain calibration steps each take oneconversion cycle to complete. At the end of the cal-ibration step, the cali

CS5525 CS552618 DS202F5VREF- as shown in Figure 12. For any input rangeother than the 2.5 V range, the modulator gain errorcan not be completely calib

CS5525 CS5526DS202F5 19Assuming a system can provide two known voltag-es, equations can allow the user to manually com-pute the calibration register’s

CS5525 CS55262 DS202F5ANALOG CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND, NBV = -2.1 V, FCLK = 32.768 kHz, OWR (Outp

CS5525 CS552620 DS202F5the input signal can be reduced to the point inwhich the gain register reaches its upper limit of 2.0(decimal) [FFFFFF Hex] (th

CS5525 CS5526DS202F5 21sion. The user would then issue 8 SCLKs (withSDI = logic 0) to clear the SDO flag. Upon the fall-ing edge of the 8th SCLK, th

CS5525 CS552622 DS202F5Digital FilterThe CS5525/26 have eight different linear phasedigital filters which set the output word rates(OWRs) as stated in

CS5525 CS5526DS202F5 23the conversion data bits can be completely erroneous.The OD flag bit will be cleared to logic 0 when themodulator becomes stabl

CS5525 CS552624 DS202F5PIN DESCRIPTIONSClock GeneratorXIN; XOUT - Crystal In; Crystal Out, Pins 9, 10.A gate inside the chip is connected to these pin

CS5525 CS5526DS202F5 25Measurement and Reference InputsAIN+, AIN- - Differential Analog Input, Pins 3, 4. Differential input pins into the device.VRE

CS5525 CS552626 DS202F5SPECIFICATION DEFINITIONSLinearity ErrorThe deviation of a code from a straight line which connects the two endpoints of the A/

CS5525 CS5526DS202F5 27 Notes: 1. Positional tolerance of leads shall be within 0.25 mm (0.010 in.) at maximum material condition, in relation to seat

CS5525 CS552628 DS202F5Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and ar

CS5525 CS5526DS202F5 29ORDERING INFORMATION ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specified by

CS5525 CS5526DS202F5 3ANALOG CHARACTERISTICS (Continued)Notes: 9. The minimum Full-scale Calibration Range (FSCR) is limited by the maximum allowed ga

CS5525 CS552630 DS202F5REVISION HISTORY Revision Date ChangesF4 JUN 2005 Added Lead-free device ordering information.F5 AUG 2005 Revised Lead-free dev

CS5525 CS55264 DS202F55 V DIGITAL CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5 V ±5%; GND = 0;See Notes 2 and 12.))Notes: 12. All measurements performed

CS5525 CS5526DS202F5 5DYNAMIC CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V; See Note 14.))Notes: 14. All voltages with respect t

CS5525 CS55266 DS202F5SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; Input Levels: Logic 0 = 0 V, Logic 1 = VD+; C

CS5525 CS5526DS202F5 7CSSCLKt0t2t1t3t6Continuous Running SCLK Timing (Not to Scale)CSSCLKMSBMSB-1 LSBSDIt3t4t5t1t2t6SDI Write Timing (Not to Scale)CSS

CS5525 CS55268 DS202F5DETAILED DESCRIPTIONThe CS5525 and CS5526 are 16-bit and 20-bit pincompatible converters which include a chopper-stabilized inst

CS5525 CS5526DS202F5 9Figure 4 illustrates the CS5525/26 connected tomeasure ground referenced unipolar signals of apositive polarity using the 1 V, 2