Cirrus-logic CDB4270 Manuel d'utilisateur télécharger pdf (Page 22)

22 DS686DB3

CDB4270

5.4.2 CS8406 Master/Slave Select (Bit 4)

Default = 0

Function:

This bit selects CS8406 Master Mode (SCLK, LRCK are outputs) or Slave Mode (SCLK, LRCK are in-

puts). See Table 7.

5.4.3 CS8406 SDIN Format Select (Bit 3)

Default = 0

Function:

This bit selects the CS8406 SDIN format. See Table 8.

5.4.4 CS8406 SDIN Source (Bits 1:0)

Default = 01

Function:

These bits select the source of the CS8406 SDIN Signal. Table 9 shows the available settings.

TX_M/S CS8406 Master/Slave

0 CS8406 Slave Mode

1 CS8406 Master Mode

Table 7. CS8406 Master/Slave

TX_FMT CS8406 SDIN Format

0 24-bit Left-Justified

1 24-bit I²S

Table 8. CS8406 SDIN Format

TXSDIO.1 TXSDIO.0 CS8406 SDIN Source

0 0 CS4270 SDOUT

0 1 CS8416 SDOUT

1 0 SDIN from Header

11 GND

Table 9. CS8406 SDIN Source

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 49 50

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Cirrus-logic CDB4270 Manuel d'utilisateur Page 22