Cirrus-logic CS5566 Manuel d'utilisateur télécharger pdf (Page 10)

CS5566

10 DS806PP2

5/4/09

DIGITAL CHARACTERISTICS

= TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V

DIGITAL FILTER CHARACTERISTICS

= TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V

16. See Figure 4 to understand conversion timing. The 160 MCLK group delay occurs during the 354 MCLK high-power period of a

conversion cycle. See Section 3.2 Power Consumption for more detail.

Parameter Symbol Min Typ Max Unit

Input Leakage Current I

--2µA

Digital Input Pin Capacitance C

-3-pF

Digital Output Pin Capacitance C

out

-3-pF

MCLK

SCLK(i)

SDO

RDY

LSBMSB

Figure 5. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale)

Parameter Symbol Min Typ Max Unit

Group Delay (Note 16) - - 160 - MCLKs

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 29 30

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Cirrus-logic CS5566 Manuel d'utilisateur Page 10