Cirrus-logic CS5464 Manuel d'utilisateur

Copyright  Cirrus Logic, Inc. 2011(All Rights Reserved)http://www.cirrus.comCS5464Three-channel, Single-phase Power/Energy ICFeatures & Descripti

CS546410 DS682F3DIGITAL CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• Typi

CS5464DS682F3 11SWITCHING CHARACTERISTICS• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.• Ty

CS546412 DS682F3t1t2t3t4t5MSBMSB-1LSBMSBMSB-1LSBMSBMSB-1LSBMSBMSB-1LSBCommand Time 8 SCLKs High Byte Mid Byte Low ByteCSSCLKSDIt10t9RESETSDOSCLKCSLast

CS5464DS682F3 13SWITCHING CHARACTERISTICS (Continued)Notes: 19. Pulse output timing is specified at DCLK = 4.096 MHz, E2MODE = 0, and E3MODE[1:0] = 0.

CS546414 DS682F34. SIGNAL PATH DESCRIPTION The data flow for voltage and current measurement andthe other calculations are shown in Figures 3, 4, an

CS5464DS682F3 154.4 DC Offset and Gain CorrectionThe system and chip inherently have gain and offset er-rors which can be removed using the gain and

CS546416 DS682F34.8 Power and Energy ResultsThe instantaneous voltage and current samples aremultiplied to obtain the instantaneous power (P1, P2)(se

CS5464DS682F3 175. PIN DESCRIPTIONS5.1 Analog PinsThe CS5464 has three differential inputs: VINIIN1,and IIN2 are the voltage, current1, and curr

CS546418 DS682F35.2.5 Serial InterfaceThe CS5464 provides 5 pins, SCLK, SDI, SDO, CS, andMODE for communication between a host microcon-troller or se

CS5464DS682F3 196. SETTING UP THE CS54646.1 Clock DividerThe internal clock to the CS5464 needs to operatearound 4 MHz. However, by using the interna

CS54642 DS682F3TABLE OF CONTENTS1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CS546420 DS682F3lists the functions of E3 as controlled by E3MODE[1:0]in the Modes register when E1MODE is not enabled.When both E2MODE bits are high,

CS5464DS682F3 21For each enabled input channel, the measured value isrectified and compared to the associated level register.Over the duration window,

CS546422 DS682F37. USING THE CS54647.1 InitializationThe CS5464 uses a power-on-reset circuit (POR) toprovide an internal reset until the analog volt

CS5464DS682F3 237.4 Command InterfaceCommands and data are transferred most-significant bit(MSB) first. Figure 1 on page 12, defines the serial portt

CS546424 DS682F37.6 CommandsAll commands are 1 byte (8 bits) long. Many command values are unused and should NOT be written by the application progr

CS5464DS682F3 257.6.4 Calibration The CS5464 can perform gain and offset calibrations using either DC or AC signals. Proper input levels must be appl

CS546426 DS682F37.6.5 Register Read and Write Read and Write commands provide access to on-chip registers. After a Read command, the addressed data c

CS5464DS682F3 27Page1 RegistersAddressRA[4:0] Name Description0 00000 I1OFFCurrent DC Offset Channel 11 00001 I1GAINCurrent Gain Channel 12 00010 V1OF

CS546428 DS682F38. REGISTER DESCRIPTIONS1. “Default” = bit states after power-on or reset2. DO NOT write a “1” to any unpublished register bit.3. DO N

CS5464DS682F3 298.2.2 Instantaneous Current (I1, I2), Voltage (V1, V2), and Power (P1, P2)Address: 1 (I1), 2 (V1), 3 (P2), 7 (I2), 8 (V2), 9 (P2)I1 (

CS5464DS682F3 35.1.4 Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175.1.5 Voltage Reference Output .

CS546430 DS682F38.2.7 Peak Current (I1PEAK, I2PEAK ) and Peak Voltage (V1PEAK, V2PEAK )Address: 18 (I1PEAK), 19 (V1PEAK), 22 (I2PEAK), 23 (V2PEAK) Pe

CS5464DS682F3 318.2.12 Internal Status (Status) and Interrupt Mask (Mask)Address: 15 (Status); 26 (Mask)Default = 1 (Status), 0 (Mask)The Status reg

CS546432 DS682F38.2.13 Control (Ctrl) – Address: 28 Default = 0PC[7:0] Phase compensation for channel 2. Sets a delay in voltage relative to current

CS5464DS682F3 338.3 Page 1 Registers8.3.1 DC Offset for Current (I1OFF , I2OFF ) and Voltage (V1OFF , V2OFF )Address: 0 (I1OFF), 2 (V1OFF), 7 (I2OFF

CS546434 DS682F38.3.5 Mode Control (Modes) – Address: 16 Default = 0Ichan Chooses an energy channel to drive the EPULSE, SPULSE, and QPULSE registers

CS5464DS682F3 35E3MODE[1:0] E3 Output Mode (with E1MODE enabled)00 = Power Fail Monitor01 = Energy Sign10 = not used11 = not usedPOS Positive Energy O

CS546436 DS682F38.3.9 Cycle Count (N) – Address: 19Default = 4000Determines the number of output word rate (OWR) samples to use in calculating low-ra

CS5464DS682F3 378.3.13 Temperature Gain (TGAIN ) – Address: 22 Default = 0x2F02C3Refer to 6.13 Temperature Measurement on page 21 for more informatio

CS546438 DS682F38.3.18 System Gain (G) – Address: 28 Default = 1.25System Gain (G) is applied to all channels. By default, G = 1.25, but can be finel

CS5464DS682F3 399. SYSTEM CALIBRATION9.1 Calibration The CS5464 provides DC offset and gain calibrationthat can be applied to the voltage and current

CS54644 DS682F39.1.4 Temperature Sensor Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409.1.4.1 Temperature Offset Calibration .

CS546440 DS682F39.1.2 Gain CalibrationDuring gain calibration, a full-scale reference signalmust be applied to the meter or optionally, scaled to the

CS5464DS682F3 4110.E2PROM OPERATIONThe CS5464 can accept commands from a serialE2PROM connected to the serial interface instead of ahost microcontroll

CS546442 DS682F311. BASIC APPLICATION CIRCUITSFigure 14 shows the CS5464 configured to measurepower in a single-phase, 2-wire system while operatingin

CS5464DS682F3 4312. PACKAGE DIMENSIONSNotes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

CS546444 DS682F313. ORDERING INFORMATION 14. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specified

CS5464DS682F3 4515. REVISION HISTORY Revision Date ChangesT1 NOV 2005 Target Data SheetPP1 MAR 2006 Preliminary ReleasePP2 JAN 2007 Update to correspo

CS546446 DS682F3Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one ne

CS5464DS682F3 51. OVERVIEWThe CS5464 is a CMOS power measurement integrated circuit utilizing four  analog-to-digital convert-ers to measure line vo

CS54646 DS682F32. PIN DESCRIPTIONClock GeneratorCrystal OutCrystal In1,28XOUT, XIN — Connect to an external quartz crystal. Alternatively, an externa

CS5464DS682F3 73. CHARACTERISTICS & SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSANALOG CHARACTERISTICS• Min / Max characteristics and specificat

CS54648 DS682F3ANALOG CHARACTERISTICS (Continued)Notes: 3. Applies before system calibration.4. All outputs unloaded. All inputs CMOS level.5. Measure

CS5464DS682F3 9VOLTAGE REFERENCENotes: 8. The voltage at VREFOUT is measured across the temperature range. From these measurements the following formu