Cirrus-logic CS43L21 Manuel d'utilisateur télécharger pdf (Page 17)

DS723F1 17

CS43L21

10. After powering up the CS43L21, RESET should be held low after the power supplies and clocks are

settled.

11. See “Example System Clock Frequencies” on page 58 for typical MCLK frequencies.

12. See“Master” on page 29.

13. “MCLK” refers to the external master clock applied.

Master Mode (Note 12)

Output Sample Rate (LRCK) All Speed Modes

(Note 13)

-Hz

LRCK Duty Cycle

45 55 %

SCLK Frequency

1/t

- 64•F

SCLK Duty Cycle

45 55 %

LRCK Edge to SDIN MSB Rising Edge

d(MSB)

52 ns

SDIN Setup Time Before SCLK Rising Edge

s(SD-SK)

20 - ns

SDIN Hold Time After SCLK Rising Edge

20 - ns

Parameters Symbol Min Max Units

MCLK

128

-----------------

s(SD-SK)

MSB MSB-1

LRCK

SCLK

SDIN

s(LK-SK)

Figure 4. Serial Audio Interface Slave Mode Timing

s(SD-SK)

MSB MSB-1

LRCK

SCLK

SDIN

d(MSB)

Figure 5. Serial Audio Interface Master Mode Timing

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 63 64

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Cirrus-logic CS43L21 Manuel d'utilisateur Page 17

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