Cirrus-logic CS42518 Manuel d'utilisateur télécharger pdf (Page 81)

DS584F2 81

CS42518

10.1.4 Circuit Board Layout

Board layout and capacitor choice affect each other and determine the performance of the PLL. Figure

30 illustrates a suggested layout for the PLL filter components and for bypassing the analog supply volt-

age. The 10 µF bypass capacitor is an electrolytic in a surface-mount case A or thru-hole package. RFILT,

CFILT, CRIP, and the 0.1 µF decoupling capacitor are in an 0805 form factor. The 0.01 µF decoupling

capacitor is in the 0603 form factor. The traces are on the top surface of the board with the IC so that there

is no via inductance. The traces themselves are short to minimize the inductance in the filter path. The

VARX and AGND traces extend back to their origin and are shown only in truncated form in the drawing.

VARX

AGND

LPFLT

CFILT

RFILT

CRIP

0.1 µF

0.01 µF

10 µF

= via to ground plane

Figure 30. Recommended Layout Example

1 2 ... 76 77 78 79 80 81 82 83 84 85 86 ... 90 91

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Cirrus-logic CS42518 Manuel d'utilisateur Page 81