Cirrus-logic CS42516 Manuel d'utilisateur Page 11
- Page / 92
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
DS583F2 11
CS42516
SWITCHING CHARACTERISTICS
(T
A
= -10 to +70° C; VA=VARX = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 =
VLS, C
L
= 30 pF)
Notes:
12. After powering-up the CS42516, RST
should be held low after the power supplies and clocks are set-
tled.
13. See Table 1 on page 25 for suggested OMCK frequencies
14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.
15. Not valid when RMCK_DIV in “Clock Control (address 06h)” on page 52 is set to Multiply by 2.
16. 76.5 ns for Single-Speed and Double-Speed modes, 23 ns for Quad-Speed Mode.
Parameters Symbol Min Typ Max Units
RST Pin Low Pulse Width (Note 12)
1--ms
PLL Clock Recovery Sample Rate Range
30 - 200 kHz
RMCK Output Jitter (Note 14)
- 200 - ps RMS
RMCK Output Duty Cycle (Note 15)
45 50 55 %
OMCK Frequency (Note 13)
1.024 - 25.600 MHz
OMCK Duty Cycle (Note 13)
40 50 60 %
CX_SCLK, SAI_SCLK Duty Cycle
45 50 55 %
CX_LRCK, SAI_LRCK Duty Cycle
45 50 55 %
Master Mode
RMCK to CX_SCLK, SAI_SCLK active edge delay
t
smd
0-15ns
RMCK to CX_LRCK, SAI_LRCK delay
t
lmd
0-15ns
Slave Mode
CX_SCLK, SAI_SCLK Falling Edge to CX_SDOUT,
SAI_SDOUT Output Valid
t
dpd
- (Note 16) ns
CX_LRCK, SAI_LRCK Edge to MSB Valid
t
lrpd
-26.5ns
CX_SDIN Setup Time Before CX_SCLK Rising Edge
t
ds
10 - - ns
CX_SDIN Hold Time After CX_SCLK Rising Edge
t
dh
30 - - ns
CX_SCLK, SAI_SCLK High Time
t
sckh
20 - - ns
CX_SCLK, SAI_SCLK Low Time
t
sckl
20 - - ns
CX_SCLK, SAI_SCLK falling to CX_LRCK, SAI_LRCK
Edge
t
lrck
-25 - +25 ns
CX_SCLK
SAI_SCLK
(output)
RMCK
t
smd
t
lmd
CX_LRCK
SAI_LRCK
(output)
sckh
sckl
t
t
MSB
MSB-1
t
dpd
CX_SDOUT
SAI_SDOUT
CX_SDINx
dh
t
ds
t
lrpd
t
lrck
t
CX_SCLK
SAI_SCLK
(input)
CX_LRCK
SAI_LRCK
(input)
Figure 1. Serial Audio Port Master Mode Timing Figure 2. Serial Audio Port Slave Mode Timing
- Features 1
- General Description 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 4
- LIST OF TABLES 5
- ABSOLUTE MAXIMUM RATINGS 6
- ANALOG INPUT CHARACTERISTICS 7
- ANALOG OUTPUT CHARACTERISTICS 9
- SWITCHING CHARACTERISTICS 11
- FORMAT 13
- DC ELECTRICAL CHARACTERISTICS 14
- A (Note 28)Serial Port 15
- 2. PIN DESCRIPTIONS 16
- DS583F2 17 17
- 18 DS583F2 18
- DS583F2 19 19
- 4. APPLICATIONS 20
- 4.3 Analog Outputs 21
- 4.3.2 Interpolation Filter 21
- 4.3.4 ATAPI Specification 22
- 4.5 Clock Generation 24
- Clock Generation 24
- 4.5.2 OMCK System Clock Mode 25
- 4.5.3 Master Mode 25
- 4.5.4 Slave Mode 25
- 4.6 Digital Interfaces 26
- DS583F2 29 29
- Left Channel Right Channel 30
- CX_SDOUT 30
- SAI_SDOUT 30
- MSB LSB MSB LSB 31
- 4.6.4.1 OLM Config #1 32
- 4.6.4.2 OLM Config #2 33
- 4.6.4.3 OLM Config #3 34
- 4.6.4.4 OLM Config #4 35
- 4.6.4.5 OLM Config #5 36
- 4.7.1 SPI Mode 37
- 4.7.2 I²C Mode 38
- 4.8 Interrupts 39
- 4.9 Reset and Power-Up 39
- 5. REGISTER QUICK REFERENCE 41
- 42 DS583F2 42
- Addr Function 7 6 5 4 3 2 1 0 42
- DS583F2 43 43
- 44 DS583F2 44
- 6. REGISTER DESCRIPTION 45
- 76543210 46
- Table 5. DAC De-Emphasis 48
- Table 6. Receiver De-Emphasis 48
- Table 8. ADC One-Line Mode 49
- Table 9. DAC One-Line Mode 49
- Table 16. ATAPI Decode 60
- 7. PARAMETER DEFINITIONS 72
- 8.1 ADC Input Filter 73
- 8.2 DAC Output Filter 73
- 9.2.1.1 One-Byte Mode 75
- 9.2.1.2 Two-Byte Mode 75
- 9.3.1.1 Format Detection 76
- 10.APPENDIX C: PLL FILTER 77
- 10.1.2 Jitter Attenuation 79
- 10.1.3 Capacitor Selection 80
- 10.1.4 Circuit Board Layout 81
- COMPONENTS 82
- DS583F2 83 83
- 84 DS583F2 84
- 84
- DS583F2 85 85
- 86 DS583F2 86
- DS583F2 87 87
- 88 DS583F2 88
- 14.PACKAGE DIMENSIONS 89
- THERMAL CHARACTERISTICS 89
- 64L LQFP PACKAGE DRAWING 89
- 15.ORDERING INFORMATION 90
- 16.REFERENCES 90
- 17.REVISION HISTORY 91
- 92 DS583F2 92
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