Copyright Cirrus Logic, Inc. 2011(All Rights Reserved)http://www.cirrus.comApplication NoteCS150x & CS160x PCB LAYOUT GUIDELINES1. INTRODUCTIONT
AN3462Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to y
AN34632. PCB LAYOUTFigure 1 and Figure 2 show a schematic and layout for a 90W PFC stage. The board is a single-layer PCBwith through-hole components
AN34642.2 Placement of the CS1501 Relative to the Power Stage– The IC should be placed away from power switching devices & traces.– Placing the IC
AN34653.1 Decoupling of Sensitive Pins for CS1501PFC Controllers have certain pins that are considered noise sensitive. For the CS1501 these are:–Pin
AN34663.2 Decoupling of Sensitive Pins for CS1500IAC (pin 3) and FB (pin 4) are noise-sensitive pins. Again, care must be taken to route these signals
AN34673.3 Routing for ZCD and CS Pins for CS1501The ZCD and the CS pins are the most sensitive pins on the IC. Since the sources of these signals arec
AN34683.3.3 Option 3 This is very similar to option 2, but in this case, a 33 pF capacitor is added in parallel to a 4.7 uF VDDdecoupling capacitor. T
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