Cirrus-logic CDB53L21 Manuel d'utilisateur

Copyright © Cirrus Logic, Inc. 2006(All Rights Reserved)http://www.cirrus.comEvaluation Board for CS53L21Features Selectable Analog Inputs– Stereo Li

10 DS700DB1CDB53L212.3 ADC Volume Controls TabThe “ADC Volume Controls” tab provides high-level control of all volume settings in the ADC of theCS53L2

DS700DB1 11CDB53L212.4 Mix Volume Controls TabThe “Mix Volume Controls” tab provides high-level control of the ADC channel mix functions. Status text

12 DS700DB1CDB53L212.5 Register Maps TabThe Advanced Register Debug tab provides low-level control of the CS53L21 individual register settings.Registe

DS700DB1 13CDB53L213. HARDWARE MODE CONTROLThe CDB may be configured without the use of a software control port through the use of two switches, “FPGA

14 DS700DB1CDB53L21OscillatorMCLKLRCK/SCLKSDOUTCS53L21I/O HeaderMCLKSDOUTLRCK/SCLKCS8406OMCK(256Fs)ILRCK/ISCLKSDIN(LJ)Figure 6. Routing 4OscillatorMC

DS700DB1 15CDB53L21OscillatorMCLKLRCK/SCLKSDOUTCS53L21I/O HeaderMCLKSDOUTLRCK/SCLKCS8406OMCK(256Fs)ILRCK/ISCLKSDIN(LJ)Figure 8. Routing 8MCLKLRCK/SCL

16 DS700DB1CDB53L213.2 CS53L21 H/W ControlThe stand-alone “CS53L21 H/W Control” switch S5 controls the Hardware Mode options of the CS53L21.A descript

DS700DB1 17CDB53L214. PERFORMANCE PLOTS-180+0-170-160-150-140-130-120-110-100-90-80-70-60-50-40-30-20-10dBFS20 20k50 100 200 500 1k 2k 5k 10kHz-180+0-

18 DS700DB1CDB53L21-100-80-98-96-94-92-90-88-86-84-8220 20k50 100 200 500 1k 2k 5k 10kHz-100-66-98-96-94-92-90-88-86-84-82-80-78-76-74-72-70-68dBFS20

DS700DB1 19CDB53L21-2+0-1.8-1.6-1.4-1.2-1-0.8-0.6-0.4-0.220 20k50 100 200 500 1k 2k 5k 10kHz-2+0-1.8-1.6-1.4-1.2-1-0.8-0.6-0.4-0.2dBFS20 20k50 100 200

2 DS700DB1CDB53L21TABLE OF CONTENTS1. SYSTEM OVERVIEW ...

20 DS700DB1CDB53L215. SYSTEM CONNECTIONS AND JUMPERS CONNECTOR REF INPUT/OUTPUT SIGNAL PRESENT+5V J26 Input +5.0 V Power Supply. GND J27 Input Grou

DS700DB1 21CDB53L21 JMP LABEL PURPOSE POSITION FUNCTION SELECTEDJ31 VLSelects source of voltage for the VL supply*+1.8V Voltage source is +1.8 V regul

22 DS700DB1CDB53L216. BLOCK DIAGRAM Figure 26. Block DiagramAnalog InputSoftware Mode Control Port Hardware Mode SwitchesCS53L21S/PDIF Out (CS8406)Cl

DS700DB1 23CDB53L217. SCHEMATICSFigure 27. CS53L21 (Part of Schematic Sheet 1)

24 DS700DB1CDB53L21Figure 28. Analog I/O (Part of Schematic Sheet 1)

DS700DB1 25CDB53L21 Figure 29. S/PDIF I/O (Schematic Sheet 2)

26 DS700DB1CDB53L21Figure 30. FPGA (Schematic Sheet 3)

DS700DB1 27CDB53L21Figure 31. Level Shifters & I/O Stake Header (Schematic Sheet 4)

28 DS700DB1CDB53L21Figure 32. Control Port I/O (Schematic Sheet 5)

DS700DB1 29CDB53L21Figure 33. Power (Schematic Sheet 6)lm

DS700DB1 3CDB53L21LIST OF FIGURESFigure 1.General Configuration Tab ...

30 DS700DB1CDB53L218. BOARD LAYOUTFigure 34. Silk ScreenCDB53L21CS53L21CS53L21CS53L21

DS700DB1 31CDB53L21Figure 35. Top-Side Layer

32 DS700DB1CDB53L21Figure 36. Bottom-Side Layer

DS700DB1 33CDB53L219. REVISION HISTORY Revision ChangesDB1 Initial ReleaseContacting Cirrus Logic SupportFor all product questions and inquiries, cont

4 DS700DB1CDB53L211. SYSTEM OVERVIEW The CDB53L21 evaluation board is an excellent means for evaluating the CS53L21 ADC. Digital audio signal out-puts

DS700DB1 5CDB53L211.5 CS8406 Digital Audio TransmitterA complete description of the CS8406 transmitter (Figure 29 on page 25) and a discussion of the

6 DS700DB1CDB53L211.9 Stand-Alone Switches The “FPGA H/W Control” and “CS53L21 H/W Control” switches control all Hardware Mode options.Section 3. “Har

DS700DB1 7CDB53L212. SOFTWARE MODE CONTROLThe CDB53L21 may be used with the Microsoft Windows-based FlexGUI graphical user interface, allowing softwar

8 DS700DB1CDB53L212.1 General Configuration TabThe “General Configuration” tab provides high-level control of signal routing on the CDB53L21. This tab

DS700DB1 9CDB53L212.2 ADC Configuration TabThe “ADC Configuration” tab provides high-level control of all setup configurations for the CS53L21. Status