1Copyright Cirrus Logic, Inc. 2001(All Rights Reserved)Cirrus Logic, Inc.Crystal Semiconductor Products DivisionP.O. Box 17847, Austin, Texas 78760(
AN15010 AN150REV2to 1.0 and performing a system offset calibration,or adjusting the offset register until the scale readszero. Following this, the gai
AN150AN150REV2 11Why is the “Common mode + signal on AIN+ or AIN-” specification different for the 1X gain range?This difference is due to the fact th
AN15012 AN150REV2an output latch pin. When the GB bit is set to ‘1’,the instrumentation amplifier’s common-modevoltage is output on the A0 pin.The amp
• Notes •
AN1502 AN150REV2essary. Any offset or gain errors in the ADC itselfand the front-end analog circuitry will remain if thedevice is left uncalibrated.If
AN150AN150REV2 3number of bits in the output word (16 for theCS5531/33 and 24 for CS5532/34).Example: Using the CS5532 in the 64X unipolarrange with a
AN1504 AN150REV2of one LSB. For a 5 mV input signal when the LSBsize is 4 nV, the expected output code (decimal)from the converter would be 1,250,000.
AN150AN150REV2 5CS5531/32/33/34 datasheet lists the typical RMSnoise values for all combinations of gain range andword rate.In the 32X and 64X gain ra
AN1506 AN150REV2VA+ and VA- supply pins.What factors affect the input current on the voltage reference inputs?The input structure on the VREF pins is
AN150AN150REV2 7(FRS) bit in the configuration register?The FRS bit (bit 19 in the Configuration Register)is used to select between two different sets
AN1508 AN150REV2What is the difference between a “self” cali-bration and a “system” calibration?A self calibration uses voltages that are available to
AN150AN150REV2 9noise-free resolution (for the -BS versions of theparts) over this input range, even in the presence oflarge offset voltages.What is “
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